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p reliminary W6690 isdn s-controller publication release date: march 1998 - 1 - revision a1 table of contents-- 1. general description ................................ ................................ ................................ .......................... 4 2. features ................................ ................................ ................................ ................................ .................. 4 3. pin configurations ................................ ................................ ................................ .............................. 5 4. pin description ................................ ................................ ................................ ................................ ...... 7 5. system diagram and applications ................................ ................................ .............................. 10 6. block diagram ................................ ................................ ................................ ................................ ..... 12 7. functional descriptions ................................ ................................ ................................ ................ 12 7.1 main block functions ................................ ................................ ................................ ............................ 12 7.2 layer 1 functions descriptions ................................ ................................ ................................ ............. 13 7.2.1 s/t interface transmitter/receiver ................................ ................................ ................................ .. 13 7.2.2 receiver clock recovery and timing generation ................................ ................................ ............ 17 7.2.3 layer 1 activation/deactivation ................................ ................................ ................................ ....... 17 7.2.4 d channel access control ................................ ................................ ................................ ............... 22 7.2.5 frame alignment ................................ ................................ ................................ ............................. 22 7.2.6 multiframe synchronization ................................ ................................ ................................ ............. 25 7.2.7 test functions ................................ ................................ ................................ ................................ 27 7.3 serial interface bus ................................ ................................ ................................ .............................. 28 7.4 b channel switching ................................ ................................ ................................ ............................. 28 7.5 pcm port ................................ ................................ ................................ ................................ .............. 29 7.6 d channel hdlc controller ................................ ................................ ................................ ................. 29 7.6.1 d channel message transfer modes ................................ ................................ ............................... 30 7.6.2 reception of frames in d channel ................................ ................................ ................................ .. 31 7.6.3 transmission of frames in d channel ................................ ................................ ............................. 31 7.7 b channel hdlc controller ................................ ................................ ................................ .................. 32 7.7.1 reception of frames in b channel ................................ ................................ ................................ .. 32 7.7.3 transmission of frames in b channel ................................ ................................ ............................. 33 7.8 isa plug and play controller/micro-processor interface ................................ ................................ ....... 34 7.8.1 modes of operations ................................ ................................ ................................ ....................... 34 7.8.2 cascade structure of interrupt sources ................................ ................................ ........................... 35 8. register descriptions ................................ ................................ ................................ ..................... 38 8.1 chip control and d_ch hdlc controller ................................ ................................ .............................. 38 8.1.1 d_ch receive fifo d_rfifo read address 00h ................................ ................................ ............ 40 8.1.2 d_ch transmit fifo d_xfifo write address 01h ................................ ................................ .......... 40
p reliminary W6690 - 2 - 8.1.3 d_ch command register d_cmdr write address 02h ................................ ................................ ..... 40 8.1.4 d_ch mode register d_mode read/write address 03h ................................ ................................ . 41 8.1.5 d_ch timer register d_timr read/write address 04h ................................ ................................ .. 43 8.1.6 interrupt status register ista read-clear address 05h ................................ ............................... 43 8.1.7 interrupt mask register imask r/w address 06h ................................ ................................ ........... 44 8.1.8 d_ch extended interrupt register d_exir read clear address 07h ................................ ................ 44 8.1.9 d_ch extended interrupt mask register d_exim read/write address 08h ................................ ...... 45 8.1.10 d_ch status register d_star read address 09h ................................ ................................ ...... 45 8.1.11 d_ch receive status register d_rsta read address 0ah ................................ .......................... 46 8.1.12 d_ch sapi address mask d_sam read/write address 0bh ................................ ....................... 46 8.1.13 d_ch sapi1 register d_sap1 read/write address 0ch ................................ ............................... 46 8.1.14 d_ch sapi2 register d_sap2 read/write address 0dh ................................ ............................... 47 8.1.15 d_ch tei address mask d_tam read/write address 0eh ................................ ........................... 47 8.1.16 d_ch tei1 register d_tei1 read/write address 0fh ................................ ................................ .. 47 8.1.17 d_ch tei2 register d_tei2 read/write address 10h ................................ ................................ .. 47 8.1.18 d_ch receive frame byte count high d_rbch read address 11h ................................ ............. 47 8.1.19 d_ch receive frame byte count low d_rbcl read address 12h ................................ .............. 48 8.1.20 d_ch control register d_ctl read/write address 15h ................................ ................................ 48 8.1.21 command/indication receive register cir read address 16h ................................ .................... 49 8.1.22 command/indication transmit register cix write address 17h ................................ ................... 49 8.1.23 s/q channel receive register sqr read address 18h ................................ .............................. 50 8.1.24 s/q channel transmit register sqx write address 19h ................................ ............................. 50 8.1.25 pcm control register pctl read/write address 1ah ................................ ............................... 50 8.2. b1 hdlc controler ................................ ................................ ................................ .............................. 51 8.2.1 b1_ch receive fifo b1_rfifo read address 20h ................................ ................................ ....... 52 8.2.2 b1_ch transmit fifo b1_xfifo write address 21h ................................ ................................ .... 52 8.2.3 b1_ch command register b1_cmdr write address 22h ................................ ............................... 52 8.2.4 b1_ch mode register b1_mode read/write address 23h ................................ ............................. 53 8.2.5 b1_ch extended interrupt register b1_exir read clear address 24h ................................ ............. 54 8.2.6 b1_ch extended interrupt mask register b1_exim read/write address 25h ........... 55 8.2.7 b1_ch status register b1_star read address 26h ................................ ................................ ...... 55 8.2.8 b1_ch address mask register 1 b1_adm1 read/write address 27h ................................ ............. 56 8.2.9 b1_ch address mask register 2 b1_adm2 read/write address 28h ................................ ............. 56 8.2.10 b1_ch address register 1 b1_adr1 read/write address 29h ................................ ..................... 56 8.2.11 b1_ch address register 2 b1_adr2 read/write address 2ah ................................ .................... 56 8.2.12 b1_ch receive frame byte count low b1_rbcl read address 2bh ................................ ........... 57 8.2.13 b1_ch receive frame byte count high b1_rbch read address 2ch ................................ .......... 57 8.3. b2 hdlc controller ................................ ................................ ................................ .............................. 57
p reliminary W6690 publication release date: march 1998 - 3 - revision a1 8.4. pnp isa ................................ ................................ ................................ ................................ .............. 58 8.4.1 pnp address index register pnp_adr write address 0279h ................................ ....................... 60 8.4.2 pnp write data register pnp_wr write address 0a79h ................................ ............................... 60 8.4.3 pnp read data register pnp_rd read address 0203h-03ffh ................................ ..................... 60 8.4.4 set read data port set_rd write address 00h ................................ ................................ ........... 61 8.4.5 serial isolation ser_iso read address 01h ................................ ................................ .................. 61 8.4.6 configuration control cfg_ctl write address 02h ................................ ................................ ..... 61 8.4.7 wake[csn] wake write address 03h ................................ ................................ .......................... 62 8.4.8 resource data r_data read address 04h ................................ ................................ .................. 62 8.4.9 status register status read address 05h ................................ ................................ ................. 62 8.4.10 card select number csn read/write address 06h ................................ ................................ ..... 62 8.4.11 logical device number ldn read address 07h ................................ ................................ .......... 63 8.4.12 activate act read/write address 30h ................................ ................................ ....................... 63 8.4.13 i/o range check io_chk read/write address 31h ................................ ................................ ..... 63 8.4.14 i/o port base address [15:8] io_h read/write address 60h ................................ ........................ 63 8.4.15 i/o port base address [7:0] io_l read/write address 61h ................................ .......................... 64 8.4.16 interrup request level select irq_n read/write address 70h ................................ ..................... 64 8.4.17 interrupt request type irq_t read address 71h ................................ ................................ ........ 65 9. electrical characteristics ................................ ................................ ................................ .......... 65 9.1 absolute maximum rating ................................ ................................ ................................ .................... 65 9.2 power supply ................................ ................................ ................................ ................................ ....... 66 9.3 dc characteristics ................................ ................................ ................................ ................................ 66 9.4 switching characteristics ................................ ................................ ................................ ...................... 68 pnp isa mode bus timing ................................ ................................ ................................ ........................ 68 isa mode bus timing ................................ ................................ ................................ ................................ 68 intel mode read cycle timing ................................ ................................ ................................ .................... 69 intel mode write cycle timing ................................ ................................ ................................ .................... 69 motorola mode read cycle timing ................................ ................................ ................................ .............. 69 motorola mode write cycle timing ................................ ................................ ................................ ............. 70 pcm interface timing 1) ................................ ................................ ................................ .............................. 70 detailed pcm timing ................................ ................................ ................................ ................................ 71 eeprom timing ................................ ................................ ................................ ................................ ...... 71 9.5 ac timing test conditions ................................ ................................ ................................ ................... 73 10. package dimensions ................................ ................................ ................................ ........................ 73 10.1 68-pin plcc ................................ ................................ ................................ ................................ ....... 74 10.2 100-pin qfp ................................ ................................ ................................ ................................ ....... 75
p reliminary W6690 - 4 - 1. general description the winbond ' s single chip isdn s/t interface controller (W6690) is an all-in-one device suitable for isdn internet access. three hdlc controllers are incorporated in the chip, one for d channel and the other two for b channels. these hdlc controllers facilitate efficient access to signalling and data services. the pcm codec interface provides voice service or other services. for pc isa bus add-on card application, the built-in plug and play controller is used for automatic card identification and resource assignment. the plug and play controller can be disabled for traditional isa card applications. furthermore, an intel or motorola 8-bit micro-controller compatible interface is provided. 2. features full duplex 2b + d s/t-interface transceiver compatible with itu-t i.430 recommendation - four wire operation - received clock recovery - layer 1 activation/deactivation procedures - d channel access control - supports multiframe synchronization supports lapd protocol - flag generation/recognition - bit stuffing (zero insertion/deletion) - frame check sequence (fcs) generation/check - maskable address recognition - fifo buffer (2 x 64 bytes) two b channel hdlc controllers - maskable address recognition - bit rate options: 56 or 64 kbps - transparent or extended transparent mode - fifo buffer (2 64 bytes) per b channel two pcm codec interfaces for speech and pots application various b channel switching capabilities serial eeprom interface for isa plug and play configuration glueless isa plug and play interface for passive card application direct isa compatible or 8-bit microprocessor interfaces for active card and terminal adaptor (ta) applications +5 volt power supply advanced cmos technology low power consumption
p reliminary W6690 publication release date: march 1998 - 5 - revision a1 68-pin plcc and 100-pin qfp package 3. pin configurations epsd epsk epcs prxd ptxd pfck1 pbck vssd vdd xtal2 xtal1 pfck2 trst sx2 sx1 vdda sr2 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 36 37 38 39 40 41 42 43 35 34 33 32 31 30 29 28 27 i b c l k i r q 7 i r q 1 0 i r q 1 1 i r q 1 2 i r q 1 5 i r q 1 4 m p s e l 1 m p s e l 0 t e s t p i r q 6 i r q 5 i r q 4 r q 3 / i r q * a 0 a 1 a 2 / c s i n * d 3 / a d 3 d 2 / a d 2 v d d v s s d d 4 / a d 4 d 5 / a d 5 d 6 / a d 6 d 7 / a d 7 v s s a s r 1 d 1 / a d 1 d 0 / a d 0 n o w s * a 1 5 a 1 4 a 1 3 a 1 2 a3 a4 vdd vssd a5 a6 a7 a8 a9 a10 a11 cso* iorc*/ds* iowc*/rw* aen*/ale irq9 reset W6690 figure 3.1 plcc-68
p reliminary W6690 - 6 - pin configurations, continued 1 2 3 7 4 5 6 11 8 9 10 13 12 17 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 58 51 52 53 54 55 56 57 60 59 61 80 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 81 88 82 83 84 85 86 87 89 100 90 91 92 93 94 95 96 97 98 99 n c i o r c * / d s * n c n c i r q 9 a e n * / a l e a 9 v s s d a 6 i o w c * / r w * a 1 1 c s * a 1 0 a 8 a 7 v d d a 5 v s s d a 4 a 3 n c n c irq15 irq5 irq6 irq7 mpsel0 bclk irq10 irq11 irq14 irq12 mpsel1 testp nc nc a15 nows* d0/ad0 d1/ad1 d2/ad2 vssd d3/ad3 d4/ad4 d5/ad5 d6/ad6 vdd s x 1 s r 2 v d d a n c x t a l 1 p f c k 2 s x 2 t r s t vssa d7/ad7 n c x t a l 2 p t x d p f c k 1 p b c k n c n c v d d n c n c n c nc p r x d n c n c a14 a13 a12 n c n c n c n c n c n c n c n c n c r e s e t nc sr1 nc e p s k e p c s e p s d n c n c n c irq4 irq3/irq* a0 a1 a2/csin* nc W6690 figure 3.2 qfp-100
p reliminary W6690 publication release date: march 1998 - 7 - revision a1 4. pin description table 4.1 W6690 pin descriptions notation: the suffix " * " indicates an active low signal. pin name plcc-68 qfp-100 type descriptions mpsel0 mpsel1 62 63 84 85 i i these two pins select the type of micro-processor interface: mpsel1 mpsel0 function 0 0 pnp isa mode 0 1 isa mode 1 0 intel multiplexed micro- processor mode 1 1 motorola micro-processor mode testp 61 83 i used to enable normal operation (1) or enter test mode (0) a0 a1 a2/csin* a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 7 8 9 10 11 14 15 16 17 18 19 20 27 28 29 30 97 98 99 7 8 11 12 13 14 15 16 17 32 33 34 35 i pnp isa mode: 16 bit isa addresses. during pnp isa auto- configuration, a0 - a11 are needed. after configuration, a0 - a1 are used to select s/t controller's internal registers, and a2 - a15 are used by the pnp controller to generate the s/t controller's chip select signal. isa mode: a0 - a1 are used to select s/t controller's internal registers, and a2 is used as the chip select input. intel microcontroller mode: a2 is used as the chip select input. all other pins are unused. motorola microcontroller mode: a0 - a1 are used to select s controller's internal registers, and a2 is used as the chip select input. cso* 21 18 o, 4 ma pnp isa mode: this is the chip select signal generated by the internal pnp controller. other modes: unused.
p reliminary W6690 - 8 - 4. pin description, continued pin name plcc-68 qfp-100 type descriptions d0/ad0 d1/ad1 d2/ad2 d3/ad3 d4/ad4 d5/ad5 d6/ad6 d7/ad7 32 33 34 35 38 39 40 41 37 38 39 40 43 44 45 46 i/o, 12 ma pnp isa mode: 8 bit isa data bus. isa mode: 8 bit isa data bus. intel microcontroller mode: 8 bit data multiplexed with 2 bit address (ad0 - ad1). motorola microcontroller mode: 8 bit data bus reset 26 23 i pnp isa mode: isa bus reset signal, active high isa mode: isa bus reset signal, active high intel & motorola microcontroller mode: reset signal, active high trst 48 62 o, 4 ma used if terminal equipment function is enabled. the reset pulse has a pulse width of : - 125 m s when generated by the watchdog timer - 16 ms when generated by exchange awake indication code change bclk 1 91 i pnp isa & isa mode: this is the isa bus clock signal. its frequency is between 8.333 mhz and 6 mhz with a normal duty cycle of 50 %. intel & motorola microcontroller mode: not used. aen*/ale 24 21 i pnp isa mode: isa bus aen* signal isa mode: isa bus aen* signal intel microcontroller mode: ale, address latch enable. the falling edge of this signal is used to latch a valid address. motorola microcontroller mode: not used. iorc*/ds* 22 19 i pnp isa mode: isa bus i/o read signal isa mode: isa bus i/o read signal intel microcontroller mode: read signal motorola microcontroller mode: data strobe. the rising edge marks the end of a valid read or write operation.
p reliminary W6690 publication release date: march 1998 - 9 - revision a1 4. pin description, continued pin name plcc-68 qfp-100 type descriptions iowc*/rw* 23 20 i pnp isa mode: isa bus i/o write signal isa mode: isa bus i/o write signal intel microcontroller mode: write signal motorola microcontroller mode: read/write. a "1" identifies a read operation, a "0" identifies a write operation. nows* 31 36 o,4 ma pnp isa mode: isa bus no wait signal. used to shorten a i/o access cycle. normally, a 8-bit isa i/o slave cycle spends 6 clock time. the cycle can be reduced to 3 clocks when nows* is used. nows* is sampled on each falling edge of clock during the time that the isa command signal is asserted. the cycle ends when nows* is sampled low. isa mode: same as in pnp isa mode. intel & motorola microcontroller mode: not used. irq3/irq* irq4 irq5 irq6 irq7 irq9 irq10 irq11 irq12 irq14 irq15 6 5 4 3 2 25 68 67 66 64 65 96 95 94 93 92 22 90 89 88 86 87 od pnp isa mode: irq3 - 7, 9 - 12, 14 - 15 are isa bus interrupt request signals. for the selected irq pin, it is high impedance when no interrupt and is driven to low for more than 130 ns when interrupt occurs. for other unselected pins, they are open drain. isa mode: only irq3/irq* is used as the interrupt request signal. it is high impedance when no interrupt occurs and is driven to low for more than 130 ns when interrupt occurs. intel & motorola microcontroller mode: only irq3/irq* is used as the interrupt request signal. it is active low, level triggered. it is open drain when no interrupt occurs and is driven to low when interrupt occurs. xtal1 50 64 i connection for crystal input or oscillator clock input. the clock frequency is 7.68 mhz 100 ppm. xtal2 51 65 o, 4 ma connection for crystal output. left unconnected if oscillator clock is used. sr1 43 48 i s/t bus receiver input (negative) sr2 44 58 i s/t bus receiver input (positive) sx1 46 60 o s/t bus transmitter output (positive) sx2 47 61 o s/t bus transmitter output (negative) pfck1 55 69 o, 4 ma pcm port 1 frame synchronization signal of 8 khz pfck2 49 63 o, 4 ma pcm port 2 frame synchronization signal of 8 khz
p reliminary W6690 - 10 - 4. pin description, continued pin name plcc-68 qfp-100 type descriptions pbck 54 68 o pcm bit synchronization clock of 1.536 mhz ptxd 56 70 o, 4 ma pcm transmit data output with 64 kbit/s per port prxd 57 71 i pcm receive data input with 64 kbit/s per port epcs 58 72 o,4 ma serial eeprom chip select. this signal is active high. epsk 59 73 o,4 ma serial eeprom serial data clock. the frequency is below 250 khz. epsd 60 74 i/o, 4 ma serial eeprom serial data input/output. v dd 12, 36, 52 9, 41, 66 i digital power supply (5v 5 %) v dda 45 59 i analog power supply (5v 5 %) v ssd 13, 37, 53 10, 42, 67 i digital ground v ssa 42 47 i analog ground nc - 1 - 6, 24 - 31, 49 - 57, 75 - 82, 100 not connected 5. system diagram and applications typical applications include: - highly suitable for isdn internet isa passive s-card - isdn internet active s-card - isdn ta the all-in-one characteristic of W6690 makes it excellent for isdn internet-access passive card applications. the booming home pc market and powerful cpu capability make it possible to make a very low-cost isdn internet access card by using cpu's computing power and user friendly pnp isa interface. W6690 is designed for this type of scenario. W6690 integrates three hdlc controllers in the chip and interfaces to isa bus directly. all the commodities needed on the card can be reduced to a one W6690, one crystal, front end transformers and protection circuits, and an optional pcm codec if voice service is required.
p reliminary W6690 publication release date: march 1998 - 11 - revision a1 transformer & protection pcm codec 4-wire s W6690 isdn single-chip pnp s-controller figure 5.1 isdn internet passive s-card the bypass-able isa pnp circuit of W6690 also allows it to be used on active cards and external module applications. protection & transformer pcm codec W6690 ram rom controller 4-wire s figure 5.2 isdn internal active s-card protection & transformer pcm codec W6690 ram controller 4-wire s uart rs232 circuit pc pots (modem, fax, analog telephone) led & lcd display rom slic figure 5.3 isdn external ta
p reliminary W6690 - 12 - 6. block diagram the block diagram of W6690 is shown in figure 6.1 dpll and timing generator 4-wire s/t d-channel hdlc controller b-channel hdlc controller b-channel hdlc controller pcm port b-channel switching fifo fifo fifo isa plug and play circuit/ microcontroller interface isa/microcontroller interface crystal / oscillator (7.68 mhz+ 100ppm) pcm-codec interface 2b+d d serial interface bus (sib) line transceiver & ami/bin conversion b1 b2 figure 6.1 W6690 system diagram 7. functional descriptions 7.1 main block functions the functional block diagram of W6690 is shown in figure 6.1. the main function blocks are : - layer 1 function according to itu-t i.430 - serial interface bus (sib) - b channel switching - pcm port - d channel lapd controller - b channel hdlc controllers (x 2) - plug and play (pnp) circuit / micro-processor interface
p reliminary W6690 publication release date: march 1998 - 13 - revision a1 the layer 1 function includes: - s/t bus transmitter/receiver - timing recovery using digital phase locked loop (dpll) circuit - layer 1 activation/deactivation - d channel access control - frame alignment - multiframe synchronization - test functions the serial interface bus performs the multiplexing/demultiplexing of d and 2b channels. the b channel switching determines the connection between layer1, layer 2 and pcm. the pcm port provides two 64 kbps clear channels to connect to pcm codec chips. the d channel hdlc controller performs the lapd (link access procedure on the d channel) protocol according to itu-t i.441/q.921 recommendation. there are two independent b channel hdlc controllers. they can be used to support hdlc-like protocols such as internet ppp. the isa bus plug and play (pnp) circuit implements the necessary plug and play functions if enabled. if disabled, W6690 can interface to a isa bus or a 8-bit micro-processor. 7.2 layer 1 functions descriptions the layer 1 functions includes : - transmitter/receiver which conform to the electrical specifications of itu-t i.430 - receiver clock recovery and timing generation - output phase delay (deviation) compensation - layer 1 activation/deactivation procedures - d channel access control - frame alignment - multiframe synchronization - test functions 7.2.1 s/t interface transmitter/receiver according to itu-t i.430, pseudo-ternary code with 100% pulse width is used in both directions of transmission on the s/t interface. the binary "1" is represented by no line signal (zero volt), whereas a binary "0" is represented by a positive or negative pulse.
p reliminary W6690 - 14 - data transmissions on the s/t interface are arranged as frame structures. the frame is 250 m s long and consists of 48 bits, which corresponds to a 192 kbit/s line rate. each frame carries two octets of b1 channel, two octets of b2 channel and four d channel bits. therefore, the 2b+d data rate is 144 kbit/s. the frame structure is shown in figure 7.1. the frame begin is marked by a framing bit, which is followed by a dc balancing bit. the first binary "0" following the framing bit balancing bit is of the same polarity as the framing bit balancing bit, and subsequent binary zeros must alternate in polarity. figure 7.1 frame structure at s/t interface there are three wiring configurations according to i.430: point-to-point, short passive bus and extended pass bus. they are shown in figure 7.2. d l f l b 1 b 1 b 1 b 1 b 1 b 1 b 1 b 1 e d a f a n b 2 b 2 b 2 b 2 b 2 b 2 b 2 b 2 e d mb 1 b 1 b 1 b 1 b 1 b 1 b 1 b 1 e d s b 2 b 2 b 2 b 2 b 2 b 2 b 2 b 2 e 0 1 0 nt ? te d l f l b 1 b 1 b 1 b 1 b 1 b 1 b 1 b 1 l d l f a l b 2 b 2 b 2 b 2 b 2 b 2 b 2 b 2 l d l b 1 b 1 b 1 b 1 b 1 b 1 b 1 b 1 l d l b 2 b 2 b 2 b 2 b 2 b 2 b 2 b 2 l d l f l 0 1 0 te ? nt 48 bits in 250 m s 2 bits offset f = framing bit l = dc balancing bit d = d channel bit e = d channel echo bit f a = auxiliary framing bit or q-bit n = bit set to a binary value n = f a b1 = bit within b channel 1 b2 = bit within b channel 2 a = bit used for activation s = bit used for s channel m = multiframe bit
p reliminary W6690 publication release date: march 1998 - 15 - revision a1 figure 7.2 W6690 wiring configuration in the spplications W6690 te tr tr nt 1000 m (a) point-to-point configuration tr tr nt 100~200 m (b) short passive bus configuration W6690 te1 W6690 te8 . . . . . 10m tr tr nt 100~200 (c) extended passive bus configuration W6690 te1 W6690 te8 . . . . 10m 50m tr: terminating resistor
p reliminary W6690 - 16 - the transmitter and receiver are implemented by differential circuits to increase signal to noise ratio (snr). the nominal differential line pulse amplitude at 100 w termination is 750 mv, zero to peak. transformers with 2:1 turn ration are needed at transmitter and receiver for voltage level translation and dc isolation. to meet the electrical characteristic requirements in i.430, some additional circuits are needed. at the transmitter side, the external resistors (22 to 47 w ) are used to adjust the output pulse amplitude and to meet the transmitter active impedance ( 3 20 w when transmitting binary zeros). at the receiver side, the 1.8 k w resistors protect the device inputs, while the 10 k w resistors (1.8 k w +8.2 k w ) limit the peak current in impedance tests. the diode bridge is used for overvoltage protection. figure 7.3 external transmitter circuitry figure 7.4 external receiver circuitry after hardware reset, the receiver may enter power down state to save power. in thist state, the internal clocks are turned off, but the analog level detector is still active to detect signal coming from the s interface. the power down state is left either by non-info 0 signal from s interface or c/i command from micro-processor. sx1 sx2 22-47 w 22-47 w gnd o v dd 2:1 100 sr1 sr2 1.8k w 1.8k w gnd o v dd 8.2k w 8.2k w 2:1 100 w
p reliminary W6690 publication release date: march 1998 - 17 - revision a1 7.2.2 receiver clock recovery and timing generation a digital phase locked loop (dpll) circuit is used to derive the receive clock from the received data stream. this dpll uses a 7.68 mhz clock as reference. according to i.430, the transmit clock is delayed by 2 bit time from the receive clock. the "total phase deviation input to output" is -7% to +15% of a bit period. in some cases, delay compensation may be needed to meet this requirement (see ops1 - 0 bits in d_ctl register). table 7.1 output phase delay compensation table ops1 ops0 effect 0 0 no phase delay compensation 0 1 phase delay compensation 260 ns 1 0 phase delay compensation 520 ns 1 1 phase delay compensation 1040 ns the pcm output clocks (pfck1-2, pbck) are synchronous to the s-interface timing. 7.2.3 layer 1 activation/deactivation the layer 1 activation/deactivation procedures are implemented by a finite state machine. the state transitions are triggered by signals received at s interface or commands issued from micro-processor. the state outputs signals to s interface and indication to micro-processor. the cix register is used by micro-processor to issue command, and the cir register is used by micro-processor to receive indication. some commands are used for special purposes. they are "layer 1 reset", "analog loopback", "send continuous zeros" and "send single zero". 7.2.3.1 states descriptions and command/indication codes f3 deactivated without clock this is the "deactivated" state of itu-t i.430. the receive line awake unit is active except during a hardware reset pulse. after reset, once the indication "1111" has been read out, internal clocks will turn off and stay at this state if info 0 is received on the s line. the turn off time is approximate 93 ms. the command eck must be issued to activate the clocks. f3 deactivated with clock this state is identical to "f3 deactivated without clock" except the internal clocks are enabled. the state is entered by a eck command. the clocks are enabled approximately 0.5 ms to 4 ms after the eck command, depending on the crystal capacitances. (it is about 0.5 ms for 12 to 33 pf capacitance).
p reliminary W6690 - 18 - f3 awaiting deactivation the W6690 enters this state after receiving info 0 (in states f5 to f8) for 16ms (64 frames). this time constant prevents spurious effect on s interface. any non-info 0 signal on the s interface causes transition to "f5 identifying input" state. if this transition does not occur in a specific time (500 - 1000 ms), the micro-processor may issue drc or eck command to deactivate layer 1. f4 awaiting signal this state is reached when an activate request command has been received. in this state, the layer 1 transmits info1 and info 0 is received from the s interface. the software starts timer t3 of i.430 when issuing activate request command. the software deactivates layer 1 if no signal other than info 0 has been received on s interface before expiration of t3. f5 identifying input after the receipt of any non-info 0 signal from nt, the W6690 ceases to transmit info 1 and awaits identification of info 2 or info 4. this state is reached at most 50 m s after a signal different from info 0 is present at the receiver of the s interface. f6 synchronized when W6690 receives an activation signal (info 2), it responds with info 3 and waits for normal frames (info 4). this state is reached at most 6 ms after an info 2 arrives at the s interface (in case the clocks were disabled in "f3 deactivated without clock"). f7 activated this is the normal active state with the layer 1 protocol activated in both directions. from state "f6 synchronized", state f7 is reached at most 0.5 ms after reception of info 4. from state "f3 deactivated without clock" with the clocks disabled, state f7 is reached at most 6 ms after the W6690 is directly activated by info 4. f8 lost framing this is the state where the W6690 has lost frame synchronization and is awaiting resynchronization by info 2 or info 4 or deactivation by info 0. special states: analog loop initiated on enable analog loop command, info 3 is sent by the line transmitter internally to the line receiver (info 0 is sent to the line). the receiver is not yet synchronized. analog loop activated the receiver is synchronized on info 3 which is looped back internally from the transmitter. the indication 'ti" or "ati" is sent depending on whether or not a signal different from info 0 is detected on the s interface. send continuous pulses a 96 khz continuous pulse with alternating polarities is sent. send single pulses a 2 khz isolated pulse with alternating polarities is sent. layer 1 reset
p reliminary W6690 publication release date: march 1998 - 19 - revision a1 a layer 1 reset command forces the transmission of info 0 and disables the s line awake detector. thus activation from nt is not possible. there is no indication in reset state. the reset state can be left only with eck command. table 7.2 layer 1 command codes command sym. code description enable clock eck 0000 enable internal clocks layer 1 reset rst 0001 layer 1 reset send continuous pulses scp 0100 send continuous pulses at 96 khz send single pulses ssp 0010 send isolated pulses at 2 khz activate request at priority 8 ar8 1000 activate layer 1 and set d channel priority level to 8 activate request at priority 10 ar10 1001 activate layer 1 and set d channel priority to 10 enable analog loopback eal 1010 enable analog loopback deactivate layer 1 drc 1111 deactivate layer 1 and disable internal clocks table 7.3 layer 1 indication codes indication sym. code descriptions clock enabled ce 0111 internal clocks are enabled deactivate request downstream drd 0000 deactivation request by s interface, i.e info 0 received level detected ld 0100 signal received, receiver not synchronous activate request downstream ard 1000 info 2 received test indication ti 1010 analog loopback activated or continuous zeros or single zeros transmitted awake test indication ati 1011 level detected during test function activate indication with priority class 1 ai8 1100 info 4 received, d channel priority is 8 or 9 activate indication with priority class 2 ai10 1101 info 4 received, d channel priority is 10 or 11 clock disabled cd 1111 layer 1 deactivated, internal clocks are disabled 7.2.3.2 state transition diagrams the followings are the state transition diagrams which implement the activation/deactivation state matrix in i.430 (table 5/i.430). the "command" and "s receive" entries in each state octagon keeps the state, the "indication" and "s transmit" entries in each state octagon are the state outputs. for example, at "f3 deactivated with clock" state, the layer 1 will stay at this state if the command is "eck" and the info 0 is received on s interface. at this state, it provides "ce" indication to the micro-processor and transmits info 0 on s interface. a "ar8/10" command causes transition to f4 and non-info 0 signal causes transition to f5. note that the command code writtern by the micro- processor in cix register and indication code written by layer 1 in cir register are transmitted repeatedly until a new code is written.
p reliminary W6690 - 20 - figure 7.5 layer 1 activation/s diagram - normal mode state com ind s receive s trans. f4 await. signal ar8/10 ce i0 i1 f5 ident. input ^rst 1) ld any 2) i0 f6 synchronized ^rst 1) ard i2 i3 f7 activated ar8/10 ai8/10 i4 i3 f8 lost framing ^rst 1) ld any 2) i0 f3 deact w/o clk drc cd i0 i0 f3 deact with clk eck ce i0 i0 f3 await. deact. ar8/10 drd i0 i0 notes : 1. "^rst" means "not layer 1 reset command". 2. "any" means any signal other than i0, which has not yet been determined. 3. "^i0" means any signal other than i0. notation ar8/1 ar8/10 drc eck drc drc eck eck ^i0 3) ^i0 3) ^i0 3) ^i0 3) i0 i0 i0 i0 i2 i4 i2 i4 lost framing i4 i2 lost framing
p reliminary W6690 publication release date: march 1998 - 21 - revision a1 figure 7.6 layer 1 activation/deactivation state diagram - special mode state com ind s receive s trans. reset rst none ignored i0 send cont. pulses scp ti ignored ic 3) send sing. pulses ssp ti ignored is 4) ana. loop init. eal ce ignored i3 5) ana. loop act. eal ti/ati ignored i3 5) rst scp ssp eal eck y 2) y 2) y 2) y 2) i3 5) ^i3 5) notation: notes: 1. rst can be issued at any state, while scp, scz and eal can be issued only at f3 or f7. 2. y is one of the commands : eck, drc, rst. 3. continuous pulses at 96 khz. 4. isolated pulses at 2 khz. 5. the info 3 is transmitted internally only.
p reliminary W6690 - 22 - 7.2.4 d channel access control the d channel access control includes collision detection and priority management. the collision detection is always enabled. the priority management procedure as specified in itu-t i.430 is fully implemented in W6690. a collision is detected if the transmitted d bit and the received echo bit do not match. when this occurs, d channel transmission is immediately stopped and the echo channel is monitored to attempt the next d channel access. the layer 1 module uses an internal signal to inform layer 2 module of the collision condition (drdy bit goes inactive in cir register). there are two priority classes : class 1 and class 2. within each class, there are normal and lower priority levels. table 7.4 d priority classes normal level lower level priority class 1 8 9 priority class 2 10 11 the selection of priority class is via the ar8/ar10 command. the following table summarizes the commands/indications used for setting the priority classes : table 7.5 d priority commands/indications command sym. code remarks activate request, set priority 8 ar8 1000 activation command, set d channel priority to 8 activate request, set priority 10 ar10 1001 activation command, set d channel priority to 10 indication abbr. remarks activate indication with priority 8 ai8 1100 info 4 received, d channel priority is 8 or 9 activate indication with priority 10 ai10 1101 info 4 received, d channel priority is 10 or 11 7.2.5 frame alignment the following sections describe the behavior of W6690 in respect to the cts-2 conformance test procedures for frame alignment. please refer to etsi-tm3 appendix b1 for detailed descriptions. 7.2.5.1 fainfa_1fr this test checks if te does not lose frame alignment on receipt of one bad frame. the pattern for the bad frame is defined as ix_96 khz. this pattern consists of alternating pulses at 96 khz during the whole frame.
p reliminary W6690 publication release date: march 1998 - 23 - revision a1 info 4 info 4 info 4 info 3 info 3 info 3 info 3 device settings result W6690 none pass 7.2.5.2 fainfb_1fr this test checks if te does not lose frame alignment on receipt of one ix_i4noflag frame which has no framing and balancing bit. the following figure indicates one possible ix_i4noflag waveform. info 4 info 4 info 4 info 3 info 3 info 3 info 3 device settings result W6690 none pass 7.2.5.3 fainfd_1fr this test checks if te does not lose frame alignment on receipt of one ix-i4viol16 frame. the ix_i4viol16 frame remains at binary "1" until the first b2 bit which is bit position 16. the pulse sequences are: framing bit, balancing bit, b2 bit, m bit, s bit, balancing bit. the te should reflect the received fa bit (fa = "1") in the transmitted frame. info 4 info 4 info 4 info 3 info 3 info 3 f a = 1 i3_basic with f a = 1 ix_i4viol16 ix_96 khz ix_i4noflag i4_basic
p reliminary W6690 - 24 - device settings result W6690 none pass 7.2.5.4 fainfa_kfr this is to test the number k of ix_96 khz frames necessary for loss of frame alignment. info 4 info 4 info 3 info 3 info 3 device settings result W6690 k = 2 pass 7.2.5.5 fainfb_kfr this is to test the number k of ix_i4noflag frames necessary for loss of frame alignment. info 4 info 4 info 3 info 3 info 3 device settings result W6690 k = 2 pass i3_sfal info 0 i3_sfal info 0 ix_i4noflag i 4-basic ix_i4noflag ix_i4noflag ix_96 khz ix_96 khz ix_96 khz
p reliminary W6690 publication release date: march 1998 - 25 - revision a1 7.2.5.6 fainfd_kfr this is to test the number k of ix_i4noflag frames necessary for loss of frame alignment. info 4 info 4 info 3 info 3 device settings result W6690 k = 2 pass 7.2.5.7 faregain this is to test the number m of good frames necessary for regain of frame alignment. the te regains frame alignment at m+1 frame. the W6690 achieves synchronization after 5 frames, i.e m = 4. 1 2 3 4 5 6 7 info x info 4 info 4 info 4 info 4 info 4 info 4 info 4 info 3 info 3 info 3 device settings result W6690 m = 4 pass 7.2.6 multiframe synchronization as specified by itu-t i.430, the q bit is transmitted from te to nt in the position normally occupied by the auxiliary framing bit (fa) in one frame out of 5, whereas the s bit is transmitted from nt to te. the s and q bit positions and multiframe structure are shown in table 7.6. i3_sfl i3_sfal info 0 info 3 with fa = 1 f a = 1
p reliminary W6690 - 26 - the functions provided by W6690 are: - multiframe synchronization: synchronization is achived when the m bit pattern has been correctly received during 20 consecutive frames starting from frame number 1. note: criterion for multiframe synchronization is not defined in i.430 recommendation. - s bits receive and detect: when synchronization is achieved, the four received s bits in frames 1, 6, 11, 16 are stored as s1 to s4 in the sqr register respectively. a change in the recived four bits (s1-4) is indicated by an interrupt (isc in d_exir register and scc in cir register). - multiframe synchronization monitoring: multiframe synchronization is constantly monitored. the synchronization state is indicated by the msyn bit in the sqr register. - q bits transmit and f a mirroring: when multiframe synchronization is achived, the four bits q1-4 stored in the sqxr register are transmitted as the four q bits (f a -bit position) in frames 1, 6, 11 and 16. otherwise the f a bit transmitted is a mirror of the received f a -bit. at loss of synchronization, the mirroring is resumed at the next f a -bit. - the multiframe synchronization can be disabled by setting mfd bit in the d_mode register. - according to i.430 recommendation, the s/q channel can be used as operation and maintenance signalling channel. at transmitter, a s/q code for a message shall be repeated at least six times or as many as necessary to obtain the desired response. at receiver, a message shall be considered received only when the proper codes is received three consecutive times. table 7.6 multiframe structure in s/t interface frame number nt-to-te f a -bit position nt-to-te m bit nt-to-te s bit te-to-nt f a -bit position 1 2 3 4 5 one zero zero zero zero one zero zero zero zero s1 zero zero zero zero q1 zero zero zero zero 6 7 8 9 10 one zero zero zero zero zero zero zero zero zero s2 zero zero zero zero q2 zero zero zero zero 11 12 13 14 15 one zero zero zero zero zero zero zero zero zero s3 zero zero zero zero q3 zero zero zero zero
p reliminary W6690 publication release date: march 1998 - 27 - revision a1 table 7.6 multiframe structure in s/t interface, continued frame number nt-to-te f a -bit position nt-to-te m bit nt-to-te s bit te-to-nt f a -bit position 16 17 18 19 20 one zero zero zero zero zero zero zero zero zero s4 zero zero zero zero q4 zero zero zero zero 1 2 etc. one zero one zero s1 zero q1 zero 7.2.7 test functions the W6690 provides loop and test functions as follows: - dgital loop via dlp bit in d_mode register: in the layer 2 block, the transmitted 2b+d data are internally looped (from hdlc transmitter to hdlc receiver), and in the pcm ports, the transmitted b channels are internally looped (from pcm inputs to pcm outputs). the clock timings are generated internally and are independent of the s bus timing. this loop function is used for test of pcm and higher layer functions, excluding layer 1. after hardware reset, W6690 will power down if s bus is not connected or if there is no signal on the s bus. in this case, the c/i command eck must be issued to power up the chip. - aalog loop via the c/i command eal: the analog s interface transmitter is internally connected to the s interface receiver. when the receiver has synchronized itself to the internal info 3 signal, the message "test indication" or "awake test indication" is delivered to the cir register. no signal is transmitted over the s interface. in this mode, the s interface awake detector is enabled. therefore if a level (info 2/ info 4) is detected on the s interface, this will be reported by the "awake test indication (ati)" indication. - rmote loopback via rlp bit in d_mode register: the digital 2b data received from the s interface receiver is loopbacked to the s interface transmitter. the d channel is not looped. when rlp is enabled, layer 1 d channel is connected to hdlc port and dlp cannot be enabled. - tansmission of special test signals via layer 1 command : * send single pulses (ssp): to send isolated single pulses of alternating polarity, with pulse width of one bit time, 250 m s apart, with a repetition frequency of 2 khz. * send continuous pulses (scp): to send continuous pulses of alternating polarity, with pulse width of bit time. the repetition frequency is 96 khz.
p reliminary W6690 - 28 - figure 7.7 ssp and scp test signals 7.3 serial interface bus the 192 kbps s/t interface signal consists of two b channels (64 kbps each), one d channel (16 kbps) and other control signals. the multiplexing/demultiplexing functions are carried out in the serial interface bus (sib) block. in addition, the b1 and b2 channels can be individually set to carry 64 kbps or 56 kbps traffic. 7.4 b channel switching each b channel in s/t bus can be individually programmed to connect to one of the three data ports: b channel hdlc controller , pcm port 1 or pcm port 2. in addition, the pcm ports can be programmed to connect to the b channel hdlc controller for voice recording/ retrieving from main memory in answering machine applications. in this case, only extended transparent mode can be used. the switching matrix is controlled by pxc bit in pctl register and bsw1 - 0 bits in b1_mode and b2_mode registers as follows: a special mode is provided (bsw1 - 0 = 11b) in which case the pcm port can receive data from layer 1 and the hdlc receiver can receive data from pcm port simultaneously. 250 us (a) single pulses (b) continuous pulses layer 1 hdlc b1 layer 1 hdlc b2 pcm1 pcm2 01 00 10 01 00 10 0 0 1 1 bsw1-0 pxc
p reliminary W6690 publication release date: march 1998 - 29 - revision a1 7.5 pcm port there are two pcm ports in W6690. each pcm port can connect to a pcm codec filter chip. these two pcm ports share the same signals except for the frame synchronization clocks. the frame synchronization clocks (pfck1-2) are 8 khz and the bit synchronization clock (pbck) is 1.536 mhz. the bit data rate is 64 kbps per port. 7.6 d channel hdlc controller there are two hdlc protocols that are used for isdn layer 2 functions: lapd and lapb. their frame formats are shown below. lapb modulo 8: flag (1 octet) address (1octet) control (1octet) information (0 or n octets) fcs (2 octets) flag control field bits 7 6 5 4 3 2 1 0 i frame n(r) p n(s) 0 s frame n(r) p/f s s 0 1 u frame m m m p/f m m 1 1 lapb modulo 128: flag (1 octet) address (1octet) control (1 or 2 octets) information (0 or n octets) fcs (2 octets) flag 1st octet 2nd octet control field bits 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 i frame n(s) 0 n(r) p s frame x x x x s s 0 1 n(r) p/f u frame m m m p/f m m 1 1
p reliminary W6690 - 30 - lapd: modulo 128 only flag (1 octet) address (2 octets) control (2 octets) information (0 or n octets) fcs (2 octets) flag (1 octet) 1st octet 2nd octet control field bits 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 i frame n(s) 0 n(r) p/f s frame 0 0 0 0 s s 0 1 n(r) p/f u frame m m m p/f m m 1 1 7.6.1 d channel message transfer modes the d channel hdlc controller operates in transparent mode. chracteristics: - receive frame address recognition - address comparison maskable bit-by-bit - flag generation/deletion - zero bit insertion/deletion - frame check sequence (fcs) generation/ check with crc_itu-t note: the lapd protocol uses the crc_itu-t for frame check sequence. the polynominal is x 16 + x 12 + x 5 + 1. for address recognition, the W6690 provides four programmable registers for individual sapi and tei values, sap1-2 and tei1-2, plus two fixed values for group sapi and tei, sapg and teig. the sapg equals feh or fch which corresponds to sapi = 63 for layer management procedure. the teig equals ffh which corresponds to tei = 127 for automatic tei assignment procedure. the address combinations are: - sap1 + tei1 - sap1 + ffh - sap2 + tei2 - sap2 + ffh - feh (fch) + tei1 - feh (fch) + tei2 - feh (fch) + ffh the receive frame address comparisons can be disabled (masked) per bit basis with the d_sam and d_tam registers, but comparisons with the sapg or teig cannot be disabled.
p reliminary W6690 publication release date: march 1998 - 31 - revision a1 7.6.2 reception of frames in d channel a 64-byte fifo is provided in the receive direction. the data movement between receive fifo and micro-processor is handled by interrupts. there are two interrupt sources: receive message ready (d_rmr) and receive message end (d_rme). the d_rmr interrupt indicates that at least 32 bytes of data have been received and the message/ frame is not ended. upon d_rmr interrupt, the micro-processor reads out 32 bytes of data from the fifo. the d_rme interrupt indicates the last segment of a message or a message with length 32 bytes has been received. the length of data is less than or equal to 32 and is specified in the d_rbcl register. if the length of the last segment of message is 32, only d_rme interrupt is generated and the rbc4- 0 bits in d_rbcl register are 00000b. the data between the opening flag and the crc field are stored in d_rfifo. for lapd frame, this includes the address field, control field and information field. when a d_rmr or d_rme interrupt is generated, the micro-processor must read out the data from d_rfifo and issues the receive message acknowledgement command (d_cmdr: rack bit) to explicitly acknowledge the interrupt. the micro-processor must handle the interrupt before more than 32 bytes of data are received. this corresponds to a maximum micro-processor reaction time of 16 ms at 16 kbps data rate. if the micro-processor is late in handling the interrupt, the incoming additional bytes will result in a "data overflow" interrupt and status bit. 7.6.3 transmission of frames in d channel a 64-byte fifo is provided in the transmit direction. if the transmit fifo is ready (which is indicated by a d_xfr interrupt), the micro-processor can write up to 32 bytes of data into the fifo and use the xms command bit to start frame transmission. the hdlc transmitter sends the opening flag first and then sends the data in the transmit fifo. the micro-processor must write the address, control and information field of a frame into the transmit fifo. every time no more than 32 bytes of data are left in the transmit fifo, the transmitter generates a d_xfr interrupt to request another block of data. the micro-processor can then write further data to the transmit fifo and enables the subsequent transmission by issuing an xms command. if the data written to the fifo is the last segment of a frame, the micro-processor issues the xme (transmit message end) and xms command bits to finish the frame transmission. the transmitter then transmits the data in the fifo and appends crc and closing flag. if the micro-processor fails to respond the d_xfr interrupt within a given time (16 ms), a data underrun condition will occur. the W6690 will automatically reset the transmitter and send inter frame time fill pattern (all 1's) on d channel. the micro-processor is informed about this condition via an xdun (transmit data underrun) interrupt in d_exir register. the microprocessor must wait until transmit fifo ready (via xfr interrupt), re-write data, and issue xms command to re-transmit the data. it is possible to abort a frame by issuing a d_cmdr: xrst (d channel transmitter reset) command. the xrst command resets the transmitter and causes a transmit fifo ready condition. after the micro-processor has issued the xme command, the successful termination of transmission is indicated by an d_xfr interrupt.
p reliminary W6690 - 32 - the inter-frame time fill pattern must be all 1's, according to itu-t i.430. collisions which occur on the d channel of s interface will cause an d_exir: xcol interrupt. a xrst (transmitter reset) command must be issued and software must wait until transmit fifo ready (via xfr interrupt), re-write data, and issue xms command to re-transmit the data. 7.7 b channel hdlc controller there are two b channel hdlc controllers. each b channel hdlc controller provides two operation modes: - transparent mode characteristics: * 2 byte address field * receive address comparison maskable bit-by-bit * data between opening flag and crc (not included) stored in receive fifo * flag generation / deletion * frame check sequence generation/ check with crc_itu-t polynominal * zero bit insertion/ deletion - extended transparent mode characteristics: * all data transmitted/received without modification * no address comparison * no flag generation/ detection * no fcs generation/ check * no bit stuffing for pcm-hdlc connection, only extended transparent mode can be selected. the data rate in b channel can be set at 64 kbps or 56 kbps by the b1_mode (b2_mode): sw56 bit. 7.7.1 reception of frames in b channel a 64-byte fifo is provided in the receive direction. the receive fifo threshold can be set at 48 or 32 bytes by the bn_mode register. if the number of received data reaches the threshold, a receive message ready (rmr) interrupt will be generated. the operations for reception of frames differ in each mode: transparent mode: the received frame address is compared with the contents in receive address registers. in addition, the comparisons can be selectively masked bit-by-bit via address mask registers. comparison is disabled when the corresponding mask bit is "1". in addition, flag recognition, crc check and zero bit deletion are also performed. the result of crc check is indicated in bn_star: crce bit. the data between opening flag and crc field (not included) is stored in receive fifo. two interrupts are used for the reception of data. the rmr interrupt in bn_exir register indicates at least a threshold block of data have been put in the receive fifo. the rme interrupt in bn_exir register indicates the end of frame has been received. the
p reliminary W6690 publication release date: march 1998 - 33 - revision a1 micro-processor can read out a threshold length of data from receive fifo at rmr interrupt, or all the data in receive fifo at rme interrupt. at each rmr/ rme interrupt, micro-processor must issue a receive message acknowledgement (rack) command to explicitly acknowledge the interrupt. the micro-processor reaction time for rmr/rme interrupt depends on the fifo threshold setting and b channel data rate. for example, it is 4 ms if the fifo threshold is 32 and the b channel data rate is 64 kbps. if the micro-processor is late in handling the interrupt, the incoming additional bytes will result in a "data overflow" interrupt and status bit. extended transparent mode: in this mode, all data received are stored in the receive fifo without any modification. every time up to a threshold length of data has been stored in the fifo, a bn_rmr interrupt is generated. in this mode, there is no rme interrupt. the micro-processor must react to the rmr interrupt in time, otherwise a "data overflow" interrupt and status bit will be generated. 7.7.3 transmission of frames in b channel a 64-byte fifo is provided in the transmit direction. the fifo threshold can be set at 32 or 48 bytes. the transmitter and receiver use the same fifo threshold setting. the transmit operations differ in both modes: transparent mode: in this mode, the following functions are performed by the transmitter automatically : - flag generation - crc generation - zero bi t insertion the fields such as address, control and information are provided by the micro-processor and are stored in transmit fifo. to start the frame transmission, the micro-processor issues a xms (transmit message start) command. the transmitter requests another block of data via xfr interrupt when no more than a threshold length of data are left in the fifo.the micro-processor then writes up to a threshold length of data into the fifo and activates the subsequent transmission of the frame by a xms command too. the micro-processor indicates the end of the frame transmission by issuing xme (transmit message end) and xms commands at the same time. the transmitter then transmits all the data left in the transmit fifo and appends the crc and closing flag. after this, a xfr interrupt is generated. the inter-frame time fill pattern can be programmed to 1's or flags. during the frame transmission, the micro-processor reaction time for the xfr interrupt depends on the fifo threshold setting and b channel data rate. for example, it is 4 ms if the fifo threshold is 32 and the b channel data rate is 64 kbps. if the micro-processor fails to responds within the given reaction time, the transmit fifo will be underrun. in this case, the W6690 will automatically reset the transmitter and send the inter frame time fill pattern on b channel. the micro-processor is informed about this via a transmit data underrun interrupt (xdun bit in bn_exir register). the
p reliminary W6690 - 34 - microprocessor must wait until transmit fifo ready (via xfr interrupt), re-write data, and issue xms command to re-transmit the data. the micro-processor can abort a frame transmission by issuing a transmitter reset command (xres bit in bn_cmdr register). the xres command resets the transmitter and sends inter frame time fill pattern on b channel. it also results in a transmit pool ready condition. extended transparent mode: all the data in the transmit fifo are transmitted without any modification, i.e. no flags and crcs are inserted, and no bit stuffing is performed. transmission is started by a xms command. the transmitter requests another block of data via xfr interrupt when no more than a threshold length of data is left in the fifo. the micro-processor reacts to this condition by writing up to a threshold length of data into the transmit fifo and issues a xms command to continue the message transmission. the micro-processor reaction time depends on the fifo threshold setting and b channel data rate. for example, it is 4 ms if the fifo threshold is 32 and the b channel data rate is 64 kbps. if the micro-processor fails to responds within the given reaction time, the transmit fifo will hold no data to transmit. in this case, the W6690 will automatically reset the transmitter and send the inter frame time fill pattern on b channel. the micro-processor is informed about this via a transmit data underrun interrupt (xdun bit in bn_exir register). the microprocessor must wait until transmit fifo ready (via xfr interrupt), re-write data, and issue xms command to re-transmit the data. 7.8 isa plug and play controller/micro-processor interface 7.8.1 modes of operations the micro-processor interface provides four modes of operation: - isa bus with plug and play (pnp) capability - isa bus without pnp - 8-bit intel multiplexed address/data mode - 8-bit motorola micro-processor mode the first mode is used in systems which supports plug and play utility. in this case, the i/o ports and interrupt line are configured automatically by the system software. in second case, the configurations are done manually. the third mode is used for connection to a 8 bit intel type micro-processor and the fourth mode is used to connect a motorola type micro-processor. the plug and play resource requirements are : three contiguous i/o ports and one interrupt request line. the serial identifier and resource data are stored in a 9346/93c46 type serial eeprom. only read operation is provided by W6690. W6690 connects with this eeprom via the following diagram:
p reliminary W6690 publication release date: march 1998 - 35 - revision a1 figure 7.8 pnp isa serial eeprom connection diagram the W6690 provides two types of 8-bit micro-processor interfaces: (1) intel multiplexed address/data bus type with control signals csin*, iorc*, iowc* and ale (2) motorola type with control signals csin*, r/w*, ds* the selection is made via mpsel1-0 pins as follows: mpsel1 mpsel0 function 0 0 pnp isa mode 0 1 isa mode 1 0 intel multiplexed micro-processor mode 1 1 motorola micro-processor mode 7.8.2 cascade structure of interrupt sources the W6690 uses cascade structure to record the causes of various interrupts. the interrupt structure is shown in figure 7.9. a read of the ista register clears all the interrupts except d_exi, b1_exi and b2_exi bits. these three bits are cleared if their corresponding extended interrupt registers are cleard. b1_exi bit is cleared by reading the b1_exir register and b2_exi bit is cleared by reading the b2_exir register. reading of b1_exir or b2_exir register clears all the bits in it. the b1_exim and b2_exim registers mask the corresponding bits in the b1_exir and b2_exir registers. to clear the d_exi bit, all the bits in d_exir must first be cleared. a read of the d_exir register clears all the bits except the isc bit. the isc bit is cleared by a read of cir and sqr registers. chip select serial clock data in data out epcs epsk epsd 1.8 k w -2.2 k w W6690 serial eeprom
p reliminary W6690 - 36 - an isc interrupt may originate from - a change in the received indication code (icc bit in cir register) or - a change in the received s code (scc bit in cir register). the icc interrupt can not be disabled while the scc interrupt can be disbled by clearing the scie bit in sqx register. bits scc and icc are cleared by a read of sqr and cir. d_exim register masks the corresponding bits in d_exir register. if the d_exim: isc bit is set to one, it masks the icc and scc interrupts. the icc or scc bit is set whenever a new code is loaded in cir or sqr. but if the previous register content has not been read out in case of a code change, the new code will not be loaded. the code registers are buffered with a fifo size of two. thus if several consecutive code changes are detected, only the first and the last code is obtained at the first and second register read, respectively. for intel and motorola modes, the interrupt request pin is level triggered with low active. it stays active until all the bits in ista register are cleared. if a new status bit is set while interrupt line is asserted, the interrupt request line makes no change. this may cause problems if W6690 is connected to edge triggered interrupt controllers (because the new status bit does not cause edge transition). to solve this problem, the software can write ffh into the imask register and then write back the old value. as soon as all the mask bits are set, ista register will temporarily be cleared to zero and the interrupt request line goes inactive. when the old value is written in the mask register, interrupt request line will make an edge transition if there was a queued status bit.
p reliminary W6690 publication release date: march 1998 - 37 - revision a1 figure 7.9 W6690 interrupt structure d_exim isc xcol xdun rdov wexp texp d_exir isc xcol xdun rdov wexp texp sqx q2 q1 scie q4 q3 sqr s2 s1 scie msyn s4 s3 cir codr2 codr3 drdy icc scc codr0 codr1 irq pin imask d_exi d_xfr d_rme d_rmr b2_exi b1_exi ista d_exi d_xfr d_rme d_rmr b2_exi b1_exi b1_exim rdov rme rmr xdun xfr b1_exir rdov rme rm r xdun xfr b2_exim rdov rme rmr xdun xfr b2_exir rdov rme rmr xdun xfr
p reliminary W6690 - 38 - 8. register descriptions three 8-bit registers are used by the micro-processor to access the W6690's internal registers, excluding the pnp isa control/status registers. the internal registers are accessed by first writing the address into "device address index register", followed by a number of write and/or read operations. the "device write data register" is the destination of write data, and the "device read data register" is the destination of read data. table 8.1 register address map: device internal registers access control address pins (a1a0) access register name description 00 w dev_adr address index for device's registers 01 w dev_wr write data for device's registers 10 r dev_rd read data for device's registers table 8.2 register summary: device internal registers access control address pins (a1a0) r/w name 7 6 5 4 3 2 1 0 00 w dev_adr 01 w dev_wr 10 r dev_rd in sections 8.1 - 8.3, the term "offset address" means the value that is programmed in the dev_adr register. 8.1 chip control and d_ch hdlc controller table 8.3 register address map: chip control and d channel hdlc offset access register name description 00 r d_rfifo d channel receive fifo 01 w d_xfifo d channel transmit fifo 02 w d_cmdr d channel command register 03 r/w d_mode d channel mode control 04 r/w d_timr d channel timer control 05 r_clear ista interrupt status register 06 r/w imask interrupt mask register 07 r_clear d_exir d channel extended interrupt 08 r/w d_exim d channel extended interrupt mask
p reliminary W6690 publication release date: march 1998 - 39 - revision a1 table 8.3 register address map: chip control and d channel hdlc, continued offset access register name description 09 r d_star d channel status register 0a r d_rsta d channel receive status 0b r/w d_sam d channel address mask 1 0c r/w d_sap1 d channel individual sapi 1 0d r/w d_sap2 d channel individual sapi 2 0e r/w d_tam d channel address mask 2 0f r/w d_tei1 d channel individual tei 1 10 r/w d_tei2 d channel individual tei 2 11 r d_rbch d channel receive frame byte count high 12 r d_rbcl d channel receive frame byte count low 13 reserved 14 reserved 15 r/w d_ctl d channel control register 16 r cir command/indication receive 17 w cix command/indication transmit 18 r sqr s/q channel receive register 19 w sqx s/q channel transmit register 1a r/w pctl pcm control register table 8.4 register summary: chip control and d channel hdlc offset r/w name 7 6 5 4 3 2 1 0 02 w d_cmdr rack rrst stt xms xme xrst 03 r/w d_mode mms ract tms tee mfd dlp rlp 04 r/w d_timr cnt2 cnt1 cnt0 val4 val3 val2 val1 val0 05 r_clr ista d_rmr d_rme d_xfr d_exi b1_exi b2_exi 06 r/w imask d_rmr d_rme d_xfr d_exi b1_exi b2_exi 07 r_clr d_exir rdov xdun xcol isc texp wexp 08 r/w d_exim rdov xdun xcol isc texp wexp 09 r d_star xdow xbz drdy 0a r d_rsta rdov crce rmb 0b r/w d_sam sam7 sam6 sam5 sam4 sam3 sam2 sam1 sam0 0c r/w d_sap1 sa17 sa16 sa15 sa14 sa13 sa12 sa11 sa10 0d r/w d_sap2 sa27 sa26 sa25 sa24 sa23 sa22 sa21 sa20
p reliminary W6690 - 40 - table 8.4 register summary: chip control and d channel hdlc, continued offset r/w name 7 6 5 4 3 2 1 0 0e r/w d_tam tam7 tam6 tam5 tam4 tam3 tam2 tam1 tam0 0f r/w d_tei1 ta17 ta16 ta15 ta14 ta13 ta12 ta11 ta10 10 r/w d_tei2 ta27 ta26 ta25 ta24 ta23 ta22 ta21 ta20 11 r d_rbch vn1 vn0 lov rbc12 rbc11 rbc10 rbc9 rbc8 12 r d_rbcl rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 13 reserved 14 reserved 15 r/w d_ctl wtt1 wtt2 srst tps opc1 opc0 16 r cir qcc icc codr3 codr2 codr1 codr0 17 w cix codx3 codx2 codx1 codx0 18 r sqr msyn qcie q1 q2 q3 q4 19 w sqx qcie s1 s2 s3 s4 1a r/w pctl pxc 8.1.1 d_ch receive fifo d_rfifo read address 00h the d_rfifo has a length of 64 bytes. after a d_rmr interrupt, exactly 32 bytes are available. after a d_rme interrupt, the number of bytes available equals rbc4-0 bits in the d_rbcl register. 8.1.2 d_ch transmit fifo d_xfifo write address 01h the d_xfifo has a length of 64 bytes. after an d_xfr interrupt, up to 32 bytes of data can be written into this fifo for transmission. at the first time, up to 64 bytes of data can be written. 8.1.3 d_ch command register d_cmdr write address 02h value after reset: 00h 7 6 5 4 3 2 1 0 rack rrst stt xms xme xrst rack receive acknowledge after a d_rmr or d_rme interrupt, the processor must read out the data in d_rfifo and then sets this bit to acknowledge the interrupt.
p reliminary W6690 publication release date: march 1998 - 41 - revision a1 rrst receiver reset setting this bit resets the d_ch hdlc receiver and clears the d_rfifo data. stt start timer the d_ch hardware timer is started when this bit is set to one. the timer may be stopped by a write of the d_timr register. note that the timer must be in external mode. xms transmit message start/continue setting this bit will start or continue the transmission of a frame. the opening flag is automatically added by the hdlc controller. xme transmit message end setting this bit indicates the end of frame transmission.. the d_ch hdlc controller automatically appends the crc and the closing flag after the data transmission. note: if the frame 32 bytes, xme plus xms commands must be issued at the same time. xrst transmitter reset setting this bit resets the d_ch hdlc transmitter and clears the d_xfifo. the transmitter will send inter frame time fill pattern (which is 1's) immediately. this command also results in a transmit fifo ready condition. 8.1.4 d_ch mode register d_mode read/write address 03h value after reset: 00h 7 6 5 4 3 2 1 0 mms ract tms tee mfd dlp rlp mms message mode setting determines the message transfer mode of the d_ch hdlc controller: mms mode address bytes first byte address comparison with: second byte address comparison with: 0 transparent mode 2 d_sap1, d_sap2, sapg d_tei1, d_tei2, teig notes: 1. d_sap1, d_sap2: two programmable address values for the first received address byte; sapg = fixed value fc/feh. d_tei1, d_tei2: two programmable address values for the second received address byte; teig = fixed value ffh. 2. the first byte address comparison can be masked by d_sam register, and the second byte address comparison can be masked by d_tam register. but the comparisons with sapg and teig cannot be disabled.
p reliminary W6690 - 42 - mds = 1 is used for internal test purpose only. ract receiver active setting this bit activates the d_ch hdlc receiver. this bit can be read. the receiver must be in active state in order to receive data. tms timer mode setting sets the operating mode of the d_ch timer. in the external mode (tms = 0), the timer is controlled by the processor. it is started by setting the stt bit in d_cmdr and is stopped by a write of the d_timr register. when the timer expires, a d_exp interrupt is generated. in the internal mode (tms = 1), the timer is used for internal test purposes. it should not be selected for normal chip operation. tee terminal equipment function enable the terminal equipment function is enabled when this bit is "1". the supported functions are: - watchdog timer, enabled when tee = 1 and d_ctl: tps = 1 - exchange awake, enabled when tee = 1 and d_ctl: tps = 0 when the watchdog timer has been enabled, the micro-processor has to program the wtt1, 2 bits in a specified manner within 1024 ms to reset and restart the timer. otherwise, the timer will expire in 1024 ms and a wexp interrupt together with a 125 m s reset pulse on trst pin is generated. the exchange awake condition is initiated by c/i code change condition. a 16 ms reset pulse on trst pin is generated. switching tps bit will reset the watchdog timer. the tee bit is cleared only by a hardware reset. mfd multiframe disable this bit is used to enable or disable the multiframe structure on s/t interface : 0: multiframe is enabled 1: multiframe is disabled dlp digital loopback setting this bit activates the digital loopback function. the transmitted digital 2b+d channels are looped to the received 2b+d channels. note that after hardware reset, the internal clocks will turn off if the s bus is not connected or if there is no signal on the s bus. in this case, the c/i command eck must be issued to enable loopback function. rlp remote loopback setting this bit to "1" activates the remote loopback function. the received 2b channels from the s interface are looped to the transmitted 2b channels of s interface. the d channel is not looped in this loopback function.
p reliminary W6690 publication release date: march 1998 - 43 - revision a1 8.1.5 d_ch timer register d_timr read/write address 04h value after reset: ffh 7 6 5 4 3 2 1 0 cnt2 cnt1 cnt0 val4 val3 val2 val1 val0 cnt together with val determine the time period t2 after which a texp interrupt will be generated: t2 = cnt * 2.048 s + t1 with t1 = (val +1) * 0.064 s the timer is started by setting the stt bit in d_cmdr and will be stopped when a texp interrupt is generated or the d_timr register is written. note: if cnt is set to 7, a texp interrupt is generated periodically at every expiration of t1. this register can be read only after the timer has been started. the read value indicates the timer's current count value. in case layer 1 is not activated, a c/i command "eck" must be issued in addition to the stt command to start the timer. 8.1.6 interrupt status register ista read-clear address 05h value after reset: 00h 7 6 5 4 3 2 1 0 d_rmr d_rme d_xfr d_exi b1_exi b2_exi d_rmr d_ch receive message ready a 32-byte data is available in the d_rfifo. the frame is not complete yet. d_rme d_ch receive message end the last part of a frame with length > 32 bytes or a whole frame with length 32 bytes has been received. the whole frame length is obtained from d_rbch + d_rbcl registers. the length of data in the d_rfifo equals: data length = rbc4-0 if rbc4-0 1 0 data length = 32 if rbc4-0 = 0 d_xfr d_ch transmit fifo ready this bit indicates that the transmit fifo is ready to accept data. up to 32 bytes of data can be written into the d_xfifo. an d_xfr interrupt is generated in the following cases: - after an xms command, when 3 32 bytes of xfifo is empty - after an xms together with an xme command is iss ued, when the whole frame has been transmitted - after an xrst command - after hardware reset
p reliminary W6690 - 44 - d_exi d_ch extended interrupt this bit indicates that at least one interrupt bit has been set in d_exir register. b1_exi b1_ch extended interrupt this bit indicates that at least one interrupt bit has been set in b1_exir register. b2_exi b2_ch extended interrupt this bit indicates that at least one interrupt bit has been set in b2_exir register. note: a read of the ista register clears all bits except d_exi, b1_exi and b2_exi bits. d_exi bit is cleared when all bits in d_exir register are cleared, b1_exi bit is cleared by reading b1_exi register and b2_exi bit is cleared by reading b2_exir register. 8.1.7 interrupt mask register imask r/w address 06h value after reset: ffh 7 6 5 4 3 2 1 0 d_rmr d_rme d_xfr d_exi b1_exi b2_exi setting the bit to "1" masks the corresponding interrupt source in ista register. masked interrupt status bits are read as zero. they are internally stored and pending until the mask bits are zero. setting the d_exi, b1_exi or b2_exi bit to "1" masks all the interrupts in d_exir, b1_exir or b2_exir register, respectively. 8.1.8 d_ch extended interrupt register d_exir read clear address 07h value after reset: 00 h 7 6 5 4 3 2 1 0 rdov xdun xcol isc texp wexp rdov receive data overflow frame overflow (too many short frames) or data overflow occurs in the receive fifo. in data overflow, the incoming data will overwrite the data in the receive fifo. if rdov interrupt occurs, software has to reset the receiver and discard the data received. xdun transmit data underrun this interrupt indicates the d_xfifo has run out of data. in this case, the W6690 will automatically reset the transmitter and send the inter frame time fill pattern (all 1's) on d channel. the microprocessor must wait until transmit fifo ready (via xfr interrupt or xfa bit), re-write data, and issue xms command to re-transmit the data. xcol transmit collision this bit indicates a collision on the s-bus has been detected. a xrst command must be issued and software must wait until transmit fifo ready (via xfr interrupt), re-write data, and issue xms command to re-transmit the data.
p reliminary W6690 publication release date: march 1998 - 45 - revision a1 isc indication or s channel change a change in the layer 1 indication code or multiframe s channel has been detected. the actual value can be read from cir or sqr registers. texp d_ch timer expiration expiration occurs in the d_ch timer. the timer must be in external mode. wexp watchdog timer expiration expiration occurs in the watch dog timer. a reset pulse with 125 m s pulse width is also generated on the trst pin. see d_ctl register for watch dog timer control. 8.1.9 d_ch extended interrupt mask register d_exim read/write address 08h value after reset: ffh 7 6 5 4 3 2 1 0 rdov xdun xcol isc texp wexp setting the bit to "1" masks the corresponding interrupt source in d_exir register. masked interrupt status bits are read as zero. they are internally stored and pending until the mask bits are zero. all the interrupts in d_exir will be masked if the imask:d_exi bit is set to "1". 8.1.10 d_ch status register d_star read address 09h value after reset: 00h 7 6 5 4 3 2 1 0 xdow xbz drdy xdow transmit data overwritten at least one byte of data has been overwritten in the d_xfifo. this bit is set by data overwritten condition and is cleared only by xres command. xbz transmitter busy this bit indicates the d_hdlc transmitter is busy. the xbz bit is active from the transmission of opening flag to the transmission of closing flag. drdy d channel ready this bit indicates the status of layer 1 d channel. 0: the layer 1 d channel is not ready. no transmission is allowed. 1: the layer 1 d channel is ready. layer 2 can transmit data to layer 1.
p reliminary W6690 - 46 - 8.1.11 d_ch receive status register d_rsta read address 0ah value after reset: 20h 7 6 5 4 3 2 1 0 rdov crce rmb rdov receive data overflow a "1" indicates that the d_rfifo is overflow. the incoming data will overwrite data in the receive fifo. the data overflow condition will set both the status and interrupt bits. it is recommended that software must read the rdov bit after reading data from d_rfifo at rmr or rme interrupt. the software must abort the data and issue a rrst command to reset the receiver if rdov = 1. the frame overflow condition will not set this bit. crce crc error this bit indicates the result of frame crc check: 0: crc correct 1: crc error rmb receive message aborted a "1" means that a sequence of seven 1's was received and the frame is aborted. software must issue rrst command to reset the receiver. note: normally d_rsta register should be read by the micro-processor after a d_rme interrupt. the contents of d_rsta are valid only after a d_rme interrupt and remain valid until the frame is acknowledged via a rack bit. 8.1.12 d_ch sapi address mask d_sam read/write address 0bh value after reset: 00h 7 6 5 4 3 2 1 0 sam7 sam6 sam5 sam4 sam3 sam2 sam1 sam0 this register masks(disables) the first byte address comparison of the incoming frame. if the mask bit is "1" the corresponding bit comparisons with d_sap1, d_sap2 are disabled. comparison with sapg is always performed. note: for the lapd frame, the least significant two bits are the c/r bit and ea = 0 bit. it is suggested that the comparison with c/r bit be masked. ea = 0 for two octet address frame e.g lapd, ea = 1 for one octet address frame. 8.1.13 d_ch sapi1 register d_sap1 read/write address 0ch value after reset: 00h 7 6 5 4 3 2 1 0 sa17 sa16 sa15 sa14 sa13 sa12 sa11 sa10 this register contains the first choice of the first byte address of received frame. for lapd frame, sa17 - sa12 is the sapi value, sa11 is c/r bit and sa10 is zero.
p reliminary W6690 publication release date: march 1998 - 47 - revision a1 8.1.14 d_ch sapi2 register d_sap2 read/write address 0dh value after reset: 00h 7 6 5 4 3 2 1 0 sa27 sa26 sa25 sa24 sa23 sa22 sa21 sa20 this register contains the second choice of the first byte address of received frame. for lapd frame, sa27 - sa22 is the sapi value, sa21 is c/r bit and sa20 is zero. 8.1.15 d_ch tei address mask d_tam read/write address 0eh value after reset: 00h 7 6 5 4 3 2 1 0 tam7 tam6 tam5 tam4 tam3 tam2 tam1 tam0 this register masks(disables) the second byte address comparison of the incoming frame. if the mask bit is "1" the corresponding bit comparisons with d_tei1, d_tei2 are disabled. comparison with teig is always performed. note: for the lapd frame, the least significant bit is the ea = 1 bit. 8.1.16 d_ch tei1 register d_tei1 read/write address 0fh value after reset: 00h 7 6 5 4 3 2 1 0 ta17 ta16 ta15 ta14 ta13 ta12 ta11 ta10 ta17 - ta10 this register contains the first choice of the second byte address of received frame. for lapd frame, ta17 - ta11 is the tei value, ta10 is ea = 1. 8.1.17 d_ch tei2 register d_tei2 read/write address 10h value after reset: 00h 7 6 5 4 3 2 1 0 ta27 ta26 ta25 ta24 ta23 ta22 ta21 ta20 ta27 - ta20 this register contains the second choice of the second byte address of received frame. for lapd frame, ta27 - ta21 is the tei value, ta20 is ea = 1. 8.1.18 d_ch receive frame byte count high d_rbch read address 11h value after reset: 00h 7 6 5 4 3 2 1 0 vn1 vn0 lov rbc12 rbc11 rbc10 rbc9 rbc8
p reliminary W6690 - 48 - vn1 - 0 chip version number this is the chip version number. it is read as 00b. lov length overflow a "1" in this bit indicates 3 4097 bytes are received and the frame is not yet complete. this bit is valid only after an d_rme interrupt and remains valid until the frame is acknowledge via the rack command. rbc12 - 8 receive byte count four most significant bits of the total frame length. these bits are valid only after an d_rme interrupt and remain valid until the frame is acknowledge via the rack command. 8.1.19 d_ch receive frame byte count low d_rbcl read address 12h value after reset: 00h 7 6 5 4 3 2 1 0 rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 rbc7 - 0 receive byte count eight least significant bits of the total frame length. bits rbc4-0 also indicate the length of the data currently available in d_rfifo. these bits are valid only after an d_rme interrupt and remain valid until the frame is acknowledged via the rack command. 8.1.20 d_ch control register d_ctl read/write address 15h value after reset: 00h 7 6 5 4 3 2 1 0 wtt1 wtt2 srst tps ops1 ops0 wtt1, 2 watchdog timer trigger 1, 2 when the watchdog timer has enabled (d_mode: tee = 1 and d_ctl:tps = 1), the micro- processor has to program the wtt1, 2 bits in the following sequences within 1024 ms to reset and restart the timer. otherwise, the timer will expire after 1024 ms and a wexp interrupt together with a 125 m s reset pulse on trst pin are generated: sequence wtt1 wtt2 1 1 0 2 0 1 switching tps bit from 0 to 1 or from 1 to 0 resets the watchdog timer. srst software reset when this bit is set to "1", a software reset signal is activated. the effects of this reset signal are equivalent to the hardware reset pin reset, except that it does not reset the pnp controller. this bit is not auto-clear, the software must write "0" to this bit to exit from the reset mode. note: when srst = 1, the chip is in reset state. read or write to any of the registers is inhibited at this time. the srst bit is write only.
p reliminary W6690 publication release date: march 1998 - 49 - revision a1 tps trst reset pulse select this bit selects the source of reset pulse on trst pin. it is valid only when the terminal equipment functions are enabled. 0: exchange awake a 16 ms reset pulse is generated when the a layer 1 indication code change has been detected. 1: watchdog timer a 125 m s reset pulse is generated as a result of the watchdog timer expiration. switching tps bit from 0 to 1 or from 1 to 0 resets the watchdog timer. ops1 - 0 output phase delay compensation select1 - 0 these two bits select the output phase delay compensation. ops1 ops0 effect 0 0 no output phase delay compensation 0 1 output phase delay compensation 260 ns 1 0 output phase delay compensation 520 ns 1 1 output phase delay compensation 1040 ns 8.1.21 command/indication receive register cir read address 16h value after reset: 0fh 7 6 5 4 3 2 1 0 scc icc codr3 codr2 codr1 codr0 scc s channel change a change in the received 4-bit s channel has been detected. the new code can be read from the sqr register. this bit is cleared by a read of the sqr register. icc indication code change a change in the received indication code has beendetected. the new code can be read from the cir register. this bit is cleared by a read of the cir register. codr3 - 0 layer 1 indication code value of the received layer 1 indication code. 8.1.22 command/indication transmit register cix write address 17h value after reset: 0fh 7 6 5 4 3 2 1 0 codx3 codx2 codx1 codx0
p reliminary W6690 - 50 - codx3 - 0 layer 1 command code value of the command code transmitted from layer 2 to layer 1. 8.1.23 s/q channel receive register sqr read address 18h value after reset: 0fh 7 6 5 4 3 2 1 0 msyn scie s1 s2 s3 s4 msyn multiframe synchronization when this bit is "1", a multiframe synchronization is achived, i.e the the s/t receiver has synchronized to the received fa and m bit patterns. scie s channel change interrupt enable this bit reflects the bit written in the sqx register. s1-4 received s bits these are the s bits received in nt to te direction in frames 1, 6, 11 and 16. s1 is in frame 1, s2 is in frame 6 etc. 8.1.24 s/q channel transmit register sqx write address 19h value after reset: 0fh 7 6 5 4 3 2 1 0 scie q1 q2 q3 q4 scie s channel change interrupt enable this bit is used to enable/disable the generation of cir:scc status bit and interrupt. 0: status bit and interrupt are disabled. 1: status bit and interrupt are enabled. q1-4 transmitted q bits these are the transmitted q channels in fa bit positions in frames 1, 6, 11 and 16. q1 is in frame 1, q2 is in frame 6 etc. 8.1.25 pcm control register pctl read/write address 1ah value after reset: 00h 7 6 5 4 3 2 1 0 pxc pxc pcm cross-connect this bit determines whether or not the pcm ports are cross-connected with the b channel ports. the setting of pxc is independent of the bsw1 - 0 bits.
p reliminary W6690 publication release date: march 1998 - 51 - revision a1 pxc connection 0 pcm1 ? b1, pcm2 ? b2 1 pcm1 ? b2, pcm2 ? b1 8.2. b1 hdlc controler table 8.5 register address map: b1 channel hdlc offset access register name description 20 r b1_rfifo b1 channel receive fifo 21 w b1_xfifo b1 channel transmit fifo 22 w b1_cmdr b1 channel command register 23 r/w b1_mode b1 channel mode control 24 r_clear b1_exir b1 channel extended interrupt 25 r/w b1_exim b1 channel extended interrupt mask 26 r b1_star b1 channel status register 27 r/w b1_adm1 b1 channel address mask 1 28 r/w b1_adm2 b1 channel address mask 2 29 r/w b1_adr1 b1 channel address 1 2a r/w b1_adr2 b1 channel address 2 2b r b1_rbcl b1 channel receive frame byte count low 2c r b1_rbch b1 channel receive frame byte count high table 8.6 register summary: b1 channel hdlc offset r/w name 7 6 5 4 3 2 1 0 22 w b1_cmdr rack rrst ract xms xme xrst 23 r/w b1_mode mms itf epcm bsw1 bsw0 sw56 fts1 fts0 24 r_clr b1_exir rmr rme rdov xfr xdun 25 r/w b1_exim rmr rme rdov xfr xdun 26 r b1_star rdov crce rmb xdow xbz 27 r/w b1_adm1 ma17 ma16 ma15 ma14 ma13 ma12 ma11 ma10 28 r/w b1_adm2 ma27 ma26 ma25 ma24 ma23 ma22 ma21 ma20 29 r/w b1_adr1 ra17 ra16 ra15 ra14 ra13 ra12 ra11 ra10 2a r/w b1_adr2 ra27 ra26 ra25 ra24 ra23 ra22 ra21 ra20 2b r b1_rbcl rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 2c r b1_rbch lov rbc12 rbc11 rbc10 rbc9 rbc8
p reliminary W6690 - 52 - 8.2.1 b1_ch receive fifo b1_rfifo read address 20h the b1_rfifo is a 64-byte depth fifo memory with programmable threshold. the threshold value determines when to generate an interrupt. when more than a threshold length of data has been received, a rmr interrupt is generated. after an rmr interrupt, 48 or 32 bytes can be read out, depending on the threshold setting. in transparent mode, when the end of frame has been received, a rme interrupt is generated. after an rme interrupt, the number of bytes available is less than or equal to the threshold value. 8.2.2 b1_ch transmit fifo b1_xfifo write address 21h the b1_xfifo is a 64-byte depth fifo with programmable threshold value. the threshold setting is the same as b1_rfifo. when the number of empty locations is equal to or greater than the threshold value, a xfr interrupt is generated. after a xfr interrupt, up to 48 or 32 bytes of data can be written into this fifo for transmission. 8.2.3 b1_ch command register b1_cmdr write address 22h value after reset: 00h 7 6 5 4 3 2 1 0 rack rrst ract xms xme xrst rack receive message acknowledge after a rmr or rme interrupt, the micro-processor reads out the data in b1_rfifo, it then sets this bit to explicitly acknowledge the interrupt. rrst receiver reset setting this bit resets the b1_ch hdlc receiver. ract receiver active the b1_ch hdlc receiver is active when this bit is set to "1". this bit is write only. the receiver must be in active state in order to receive data. xms transmit message start/continue in transparent mode, setting this bit initiates the transparent transmission of b1_xfifo data. the opening flag is automatically added to the message by the b1_ch hdlc controller. zero bit insertion is performed on the data. this bit is also used in subsequent transmission of the frame. in extended transparent mode, settint this bit activates the transmission of b1_xfifo data. no flag, crc or zero bit insertion is added on the data. xme transmit message end in transparent mode, setting this bit indicates the end of the whole frame transmission. the b1_ch hdlc controller transmits the data in fifo and automatically appends the crc and the closing flag sequence in transparent mode. in extended transparent mode, setting this bit stops the b1_xfifo data transmission.
p reliminary W6690 publication release date: march 1998 - 53 - revision a1 xrst transmitter reset setting this bit resets the b1_ch hdlc transmitter and clears the b1_xfifo. the transmitter will send inter frame time fill pattern on b channel. this command also results in a transmit fifo ready condition. 8.2.4 b1_ch mode register b1_mode read/write address 23h value after reset: 00h 7 6 5 4 3 2 1 0 mms itf epcm bsw1 bsw0 sw56 fts1 fts0 mds message mode setting determines the message transfer modes of the b1_ch hdlc controller : 0: transparent mode. in re ceive direction, address comparison is performed on each frame. the frames with matched address are stored in b1_rfifo. flag deletion, crc check and zero bit deletion are performed. in transmit direction, the data is transmitted with flag insertion, zero bit insertion and crc generation. 1: extended transparent mode. in receive direction, all data are received and stored in the b1_rfifo. in transmit direction, all data in the b1_xfifo are transmitted without alteration. itf inter-frame time fill defines the inter-frame time fill pattern in transparent mode. 0: mark. the binary value "1" is transmitted. 1: flag. this is a sequence of "01111110". epcm enable pcm transmit/receive 0: disable data transmit/ receive to/from pcm port. the frame synchronization clock is held low. 1: enable data transmit/ receive to/from pcm port. the frame synchronization clock is active. bsw1 - 0 b channel switching select these two bits determine the connection in b1 channel: bsw1 bsw0 connection 0 0 layer 1 ? hdlc 0 1 layer 1 ? pcm 1 0 hdlc ? pcm 1 1 layer 1 ? pcm, pcm ? hdlc note: the connection with micro-controller is through hdlc controller. when hdlc connects with layer 1, either transparent or extended transparent mode can be used. when connecting with pcm port, the epcm bit must be set to enable pcm function.
p reliminary W6690 - 54 - sw56 switch 56 traffic 0: the data rate in b1 channel is 64 kbps. 1: the data rate in b1 channel is 56 kbps. the most significant bit in each octet is fixed at "1". note: in 56 kbps mode, only transparent mode can be used. fts1 - 0 fifo threshold select these two bits determine the b1 channel receive and transmit fifo's threshold setting. an interrupt is generated when the number of received data or the number of transmitted data reaches the threshold value. fts1 fts0 threshold (byte) 0 0 32 0 1 reserved 1 0 48 1 1 not allowed 8.2.5 b1_ch extended interrupt register b1_exir read clear address 24h value after reset: 00 h 7 6 5 4 3 2 1 0 rmr rme rdov xfr xdun rmr receive message ready at least a threshold lenth of data has been stored in the b1_rfifo. rme receive message end used in transparent mode only. the last block of a frame has been received. the frame length can be found in b1_rbch + b1_rbcl registers. the number of data available in the b1_rfifo equals frame lenth modulus threshold. the result of crc check is indicated by b1_star: crce bit. when the number of last block of a frame equals the threshold, only rme interrupt is generated. rdov receive data overflow data overflow occurs in the receive fifo. the incoming data will overwrite the data in the receive fifo. xfr transmit fifo ready this interrupt indicates that a threshold length of data can be written into the b1_xfifo. xdun transmit data underrun this interrupt occurs when the b1_xfifo has run out of data. in this case, the W6690 will automatically reset the transmitter and send the inter frame time fill pattern on b channel. the software must wait until transmit fifo ready condition (via xfr interrupt or xfa bit), re-write data, and issue xms command to re-transmit the data.
p reliminary W6690 publication release date: march 1998 - 55 - revision a1 8.2.6 b1_ch extended interrupt mask register b1_exim read/write address 25h value after reset: ffh 7 6 5 4 3 2 1 0 rmr rme rdov xfr xdun setting the bit to "1" masks the corresponding interrupt source in b1_exir register. masked interrupt status bits are read as zero when b1_exir register is read. they are internally stored and pending until the mask bits are zero. all the interrupts in b1_exir will be masked if the imask: b1_exi bit is set to "1". 8.2.7 b1_ch status register b1_star read address 26h value after reset: 20h 7 6 5 4 3 2 1 0 rdov crce rmb xdow xbz rdov receive data overflow a "1" indicates that the d_rfifo is overflow. the incoming data will overwrite data in the receive fifo. the overflow condition will set both the status and interrupt bits. it is recommended that software must read the rdov bit after reading data from d_rfifo at rmr or rme interrupt. the software must abort the data and issue a rrst command to reset the receiver if rdov = 1. crce crc error used in transparent mode only. this bit indicates the result of frame crc check: 0: crc correct 1: crc incorrect rmb receive message aborted used in transparent mode only. a "1" means that a sequence of seven 1's was received and the frame is aborted by the b1_hdlc receiver. software must issue rrst command to reset the receiver. note: bits crce and rmb are valid only after a rme interrupt and remain valid until the frame is acknowledged via rack command xdow transmit data overwritten at least one byte of data has been overwritten in the b1_xfifo. this bit is cleared only by xrst command. xbz transmitter busy the b1_hdlc transmitter is busy when xbz is read as "1". this bit may be polled. the xbz bit is active when an xms command is issued and the message has not been completely transmitted.
p reliminary W6690 - 56 - 8.2.8 b1_ch address mask register 1 b1_adm1 read/write address 27h value after reset: 00h 7 6 5 4 3 2 1 0 ma17 ma16 ma15 ma14 ma13 ma12 ma11 ma10 ma17 - 10 address mask bits used in transparent mode only. these bits mask the first byte address comparisons. if the mask bit is "1", the corresponding bit comparison with b1_adr1 is disabled. 0: unmask comparison 1: mask comparison 8.2.9 b1_ch address mask register 2 b1_adm2 read/write address 28h value after reset: 00h 7 6 5 4 3 2 1 0 ma27 ma26 ma25 ma24 ma23 ma22 ma21 ma20 ma27 - 20 address mask bits used in transparent mode only. these bits mask the second byte address comparisons. if the mask bit is "1", the corresponding bit comparison with b1_adr2 is disabled. 0: unmask comparison 1: mask comparison 8.2.10 b1_ch address register 1 b1_adr1 read/write address 29h value after reset: 00h 7 6 5 4 3 2 1 0 ra17 ra16 ra15 ra14 ra13 ra12 ra11 ra10 ra17-10 address bits used in transparent mode only. these bits are used for the first byte address comparisons. 8.2.11 b1_ch address register 2 b1_adr2 read/write address 2ah value after reset: 00h 7 6 5 4 3 2 1 0 ra27 ra26 ra25 ra24 ra23 ra22 ra21 ra20 ra27 - 20 address bits used in transparent mode only. these bits are used for the second byte address comparisons.
p reliminary W6690 publication release date: march 1998 - 57 - revision a1 8.2.12 b1_ch receive frame byte count low b1_rbcl read address 2bh value after reset: 00h 7 6 5 4 3 2 1 0 rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 rbc7 - 0 receive byte count used in transparent mode only. eight least significant bits of the total number of bytes in a received frame. these bits are valid only after a rme interrupt and remain valid until the frame is acknowledge via the rack bit. 8.2.13 b1_ch receive frame byte count high b1_rbch read address 2ch value after reset: 00h 7 6 5 4 3 2 1 0 lov rbc12 rbc11 rbc10 rbc9 rbc8 lov message length overflow used in transparent mode only. a "1" in this bit indicates a received message 3 4097 bytes. this bit is valid only after rme interrupt and is cleared by the rack command. rbc12 - 8 receive byte count used in transparent mode only. five most significant bits of the total number of bytes in a received frame. these bits are valid only after a rme interrupt and remain valid until the frame is acknowledge via the rack bit. note: the frame length equals rbc12-0. this length is between 1 to 4096. after a rme interrupt, the number of data available in b1_rfifo is frame length modulus threshold. remainder = rbc12-0 mod threshold no. of available data = remainder if remainder 1 0 or no. of available data = threshold if remainder = 0 the remainder equals rbc4 - 0 if threshold is 32. 8.3. b2 hdlc controller table 8.7 register address map: b2 channel hdlc offset access register name description 30 r b2_rfifo b2 channel receive fifo 31 w b2_xfifo b2 channel transmit fifo 32 w b2_cmdr b2 channel command register 33 r/w b2_mode b2 channel mode control 34 r_clear b2_exir b2 channel extended interrupt
p reliminary W6690 - 58 - table 8.7 register address map: b2 channel hdlc, continued offset access register name description 35 r/w b2_exim b2 channel extended interrupt mask 36 r b2_star b2 channel status register 37 r/w b2_adm1 b2 channel address mask 1 38 r/w b2_adm2 b2 channel address mask 2 39 r/w b2_adr1 b2 channel address 1 3a r/w b2_adr2 b2 channel address 2 3b r b2_rbcl b2 channel receive frame byte count low 3c r b2_rbch b2 channel receive frame byte count high table 8.8 register summary: b2 channel hdlc offset r/w name 7 6 5 4 3 2 1 0 32 w b2_cmdr rack rrst ract xms xme xrst 33 r/w b2_mode mms itf epcm bsw1 bsw0 sw56 fts1 fts0 34 r_clr b2_exir rmr rme rdov xfr xdun 35 r/w b2_exim rmr rme rdov xfr xdun 36 r b2_star rdov crce rmb xdow xbz 37 r/w b2_adm1 ma17 ma16 ma15 ma14 ma13 ma12 ma11 ma10 38 r/w b2_adm2 ma27 ma26 ma25 ma24 ma23 ma22 ma21 ma20 39 r/w b2_adr1 ra17 ra16 ra15 ra14 ra13 ra12 ra11 ra10 3a r/w b2_adr2 ra27 ra26 ra25 ra24 ra23 ra22 ra21 ra20 3b r b2_rbcl rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 3c r b2_rbch lov rbc12 rbc11 rbc10 rbc9 rbc8 the b2 channel hdlc register's definitions and functions are the same as those of b1 channel hdlc. please refer to section 9.2 for a detailed description. 8.4. pnp isa three 8-bit registers are used by the micro-processor to access the pnp registers. table 8.9 register address map: pnp auto-configuration ports isa port access register name description 0279h w pnp_adr address index for pnp registers 0a79h w pnp_wr write data for pnp register 0203h - 03ffh r pnp_rd read data for pnp register
p reliminary W6690 publication release date: march 1998 - 59 - revision a1 table 8.10 register summary: pnp auto-configuration ports isa port r/w name 7 6 5 4 3 2 1 0 0279h w pnp_adr pnp_address 0a79 w pnp_wr write_data 0203h - 03ffh r pnp_rd read_data table 8.11 register address map: pnp control and configuration registers in the following tables, the "index" is the value that is programmed in pnp_adr register. index (hex) access register name description 00 w set_rd set read_data port 01 r ser_iso serial isolation 02 w cfg_ctl configuration control 03 w wake wake[csn] 04 r r_data resource data 05 r status status 06 r/w csn card select number 07 r ldn logical device number 30 r/w act activate 31 r/w io_chk i/o range check 60 r/w io_h i/o port baseaddress [15:8] 61 r/w io_l i/o port base address [7:0] 70 r/w irq_n interrupt request level select 71 r irq_t interrupt request type table 8.12 register summary: pnp control and configuration registers index r/w name 7 6 5 4 3 2 1 0 00 w set_rd ra9 ra8 ra7 ra6 ra5 ra4 ra3 ra2 01 r ser_iso x x x x x x x x 02 w cfg_ctl x x x x x ctl2 ctl1 ctl0 03 w wake m7 m6 m5 m4 m3 m2 m1 m0 04 r r_data rsd7 rsd6 rsd5 rsd4 rsd3 rsd2 rsd1 rsd0 05 r status x x x x x x x rdy 06 r/w csn n7 n6 n5 n4 n3 n2 n1 n0 07 r ldn 0 0 0 0 0 0 0 0
p reliminary W6690 - 60 - table 8.12 register summary: pnp control and configuration registers, continued index r/w name 7 6 5 4 3 2 1 0 30 r/w act 0 0 0 0 0 0 0 act 31 r/w io_chk 0 0 0 0 0 0 ena type 60 r/w io_h ia15 ia14 ia13 ia12 ia11 ia10 ia9 ia8 61 r/w io_l ia7 ia6 ia5 ia4 ia3 ia2 ia1 ia0 70 r/w irq_n x x x x irn3 irn2 irn1 irn0 71 r/w irq_t x x x x x x high lev 8.4.1 pnp address index register pnp_adr write address 0279h value after reset: undefined 7 6 5 4 3 2 1 0 bit 7 - 0 address index this register contains the address index for the desired pnp registers. the pnp registers are accessed by first writing the address into this register, followed by a number of write and/ or read operations. this register is also the write destination of initiation key. this register is fixed at isa port 0279h. 8.4.2 pnp write data register pnp_wr write address 0a79h value after reset: undefined 7 6 5 4 3 2 1 0 bit 7 - 0 write data this register contains the write data for the register specified by the pnp_adr register. this register is fixed at isp port 0a79h. 8.4.3 pnp read data register pnp_rd read address 0203h-03ffh value after reset: undefined 7 6 5 4 3 2 1 0 bit 7 - 0 read data this register contains the read data from the register specified by the pnp_adr register. the location of this register is relocatable at 0203h - 03ffh, which is set by the set_rd register.
p reliminary W6690 publication release date: march 1998 - 61 - revision a1 8.4.4 set read data port set_rd write address 00h value after reset: undefined 7 6 5 4 3 2 1 0 ra9 ra8 ra7 ra6 ra5 ra4 ra3 ra2 ra9 - 2 read_data port address this register is used to set the isa port address of pnp_rd register. bits 7 - 0 become isa address bits 9 - 2. reads from this register are ignored. 8.4.5 serial isolation ser_iso read address 01h value after reset: undefined 7 6 5 4 3 2 1 0 x x x x x x x x bit 7 - 0 don't care this register is read only. a read to this register causes a pnp card in the isolation state to compare one bit of the board's id. 8.4.6 configuration control cfg_ctl write address 02h value after reset: undefined 7 6 5 4 3 2 1 0 x x x x x ctl2 ctl1 ctl0 bit 7 - 3 ignore these bits are not used. ctl2 control bit 2 writing a "1" to this bit causes the card to reset its csn to zero. ctl1 control bit 1 writing a "1" to this bit causes the card to enter the "wait-for-key" state, but the card's csn is preserved and the logical device configurations are not affected. ctl0 control bit 0 writing a "1" to this bit resets the logical device's configuration registers to their power-up values, but the card's csn is unaffected. this register is write only. the three control bits are automatically reset to zero by hardware after the commands execute.
p reliminary W6690 - 62 - 8.4.7 wake[csn] wake write address 03h value after reset: undefined 7 6 5 4 3 2 1 0 m7 m6 m5 m4 m3 m2 m1 m0 m 7 - 0 this register is write only. a write to this register will cause all cards that have a csn that matches the m7 - 0 to go to change from the sleep state to either the isolation state if m7 - 0 is zero or the configuration state if m7 - 0 is not zero. in addition, the pointer to the "serial identifier" is reset. 8.4.8 resource data r_data read address 04h value after reset: undefined 7 6 5 4 3 2 1 0 rsd7 rsd6 rsd5 rsd4 rsd3 rsd2 rsd1 rsd0 rsd7 - 0 resource data this register is read only. a read from this register reads the next byte of resource data. the status register must be polled until bit 0 is set before this register may be read. 8.4.9 status register status read address 05h value after reset: undefined 7 6 5 4 3 2 1 0 x x x x x x x rdy bit 7 - 1 ignore these bits are not used. rdy ready when this bit is set, it is okay to read the next data byte from the r_data register. 8.4.10 card select number csn read/write address 06h value after reset: 0 7 6 5 4 3 2 1 0 n7 n6 n5 n4 n3 n2 n1 n0 n7 - 0 card select number n7 - 0 is the card's csn, which is uniquely assigned to this card after the serial isolation process so that each card may be individually selected during a wake[csn] command.
p reliminary W6690 publication release date: march 1998 - 63 - revision a1 8.4.11 logical device number ldn read address 07h value after reset: 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 this register has a read-only value of 0, since the card has only one logical device. 8.4.12 activate act read/write address 30h value after reset: undefined 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 act act activate each logical device has one activate register. the logical device is activated when the act bit is set. bit 7 - 1 are reserved and must return zero on reads. before a logical device is activated, i/o range check must be disabled. 8.4.13 i/o range check io_chk read/write address 31h value after reset :undefined 7 6 5 4 3 2 1 0 0 0 0 0 0 0 ena type this register is used to perform a conflict check on the i/o port range programmed for use by the logical device. bits 7 - 2 are reserved and must return zero on read. ena enable i/o range check if set, i/o range check is enabled. i/o range check is valid only when the logical device is deactivated. type i/o range check drive type this bit determines the drive type in response to the i/o read of the logical device's assigned i/o range when i/o range check is in operation. 0: drive aah. 1: drive 55h. 8.4.14 i/o port base address [15:8] io_h read/write address 60h value after reset: undefined 7 6 5 4 3 2 1 0 ia15 ia14 ia13 ia12 ia11 ia10 ia9 ia8
p reliminary W6690 - 64 - this register indicates the selected i/o upper limit address bits 15 - 8 for i/o descriptor 0. when the device is activated, if there is an address match to io_l and an address match to this register, a chip select signal is generated. ia15 - 10 isa address 15 - 10 these bits are not supported since the logical device uses 10-bit address decoding. ia9 - 8 isa address 9 - 8 these two bits are the isa address bits 9 - 8. 8.4.15 i/o port base address [7:0] io_l read/write address 61h value after reset: undefined 7 6 5 4 3 2 1 0 ia7 ia6 ia5 ia4 ia3 ia2 ia1 ia0 this register indicates the selected i/o lower limit address bits 7 - 0 for i/o descriptor 0. when the device is activated, if there is an address match to io_h register and an address match to this register, a chip select is generated. ia 7 - 2 isa address 7 - 2 these bits are the isa address bits 7 - 2. ia 1 - 0 isa address 1 - 0 these bits are not supported since the logical device needs four isa ports. they are read as zeros. 8.4.16 interrup request level select irq_n read/write address 70h value after reset :undefined 7 6 5 4 3 2 1 0 x x x x irn3 irn2 irn1 irn0 bit 7 - 4 ignore irn3 - 0 interrupt level number these bits select the interrupt level number. one selects irq1, fifteen selects irq15. zero is not a valid interrupt selection and represents no interrupt selection.
p reliminary W6690 publication release date: march 1998 - 65 - revision a1 8.4.17 interrupt request type irq_t read address 71h value after reset: 02h 7 6 5 4 3 2 1 0 x x x x x x high lev bit 7 - 2 don't care high interrupt high active 0: the interrupt is low active. 1: the interrupt is high active. lev interrupt level triggered 0: the interrupt is edge triggered. 1: the interrupt is level triggered. notes: 1. this register is read only. only the edge triggered, high active type is implemented. 2. an edge triggered, high active interrupt must be programmed for isa compatibility. this means that a valid interrupt generates a low to high transition on the interrupt request line. remarks about plug and play isa specification: according to "plug and play isa specification", the following requirements must be obeyed : 1. any unimplemented memory configuration registers must return "zero" on read. 2. any unimplemented i/o configuration registers must return "zero" on read. 3. any unimplemented interrupt configuration registers must return "zero" on read. 4. any unimplemented dma configuration registers must return "four" on read. 9. electrical characteristics 9.1 absolute maximum rating parameter symbol limit values unit voltage on any pin with respect to ground v s -0.4 to v dd +0.4 v ambient temperature under bias t a 0 to 70 c maximum voltage on v dd v dd 6 v
p reliminary W6690 - 66 - 9.2 power supply the power supply is 5v 5 %. 9.3 dc characteristics t a = 0 to 70 c; v dd = 5v 5 %, v ssa = 0v, v ssd = 0v parameter sym. min. max. unit test conditions remarks low input voltage v il -0.4 0.8 v high input voltage v ih 2.0 v dd +0.4 v low output voltage v ol 0.4 v i ol = 12 ma d0 - d7 in pnp isa or isa modes high output voltage v oh 2.4 v power supply current (power down) i cc 1.5 ma v dd = 5v, inputs at v dd /v ss , no output loads except at sx1, 2 (50 w load) power supply current (operational) i cc 17 ma v dd = 5v, inputs at v dd /v ss , no output loads except at sx1, 2 (50 w load) input leakage current i li 10 m a 0v < v in < v dd to 0v all pins except sx1, 2, sr1,2 output leakage current i lo 10 m a 0v < v out < v dd to 0v all pins except sx1, 2, sr1, 2 absolute value of output pulse amplitude (v sx2 - v sx1 ) v x 2.03 2.10 2.31 2.39 v v r l = 50 w r l = 400 w sx1, 2 transmitter output current i x 7.5 13.4 ma r l = 5.6 w sx1, 2 transmitter output impedence r x 30 23 k w w inactive or during binary one during binary zero (r l = 50 w ) sx1, 2 note: due to the transformer, the load resistance seen by the circuit is four times r l .
p reliminary W6690 publication release date: march 1998 - 67 - revision a1 capacitances t a = 25 c, v dd = 5 v 5%, v ssa = 0v, v ssd = 0v, fc = 1 mhz, unmeasured pins grounded. parameter sym. min. max. unit remarks input capacitance c in 7 pf all pins except sr1, 2 i/o pin capacitance c io 7 pf all pins except sr1, 2 output capacitance against v ssa c out 10 pf sx1, 2 input capacitance c in 7 pf sr1, 2 load capacitance c l 50 pf xtal1, 2 recommended oscillator circuits crystal specifications parameter symbol values unit frequency f 7.680 mhz frequency calibration tolerance max. 100 ppm load capacitance c l max. 50 pf oscillator mode fundamental note: the load capacitance c l depends on the crystal specification. the typical values are 33 to 47 pf. external ocsillator input (xtal1) clock characteristics parameter min. max. duty cycle 1:2 2:1 50 xtal1 xtal2 51 7.68mhz c l 50 pf c l c l 50 xtal1 xtal2 51 external oscillator signal n.c. or
p reliminary W6690 - 68 - 9.4 switching characteristics pnp isa mode bus timing notes: 1. when doing plug and play operation, a[11:0] are used, otherwise a[15:0] are used. 2. when doing plug and play operation, nows* is not asserted. in other cases, nows* is asserted which causes a 3 clock cycle i/o access. isa mode bus timing t1 aen* t2 t12 t3 t4 t5 t6 t7 t8 t9 t11 t10 a<1:0> iorc* iowc nows* d<7:0> (read) d<7:0> (write) csin* t15 t16 t4 t1 aen* t2 t12 t3 t5 t6 t7 t8 t9 t10 t11 a<15:0> 1) iorc* iowc* nows* 2) d<7:0> (read) d<7:0> (write) t13 t14 cso*
p reliminary W6690 publication release date: march 1998 - 69 - revision a1 intel mode read cycle timing intel mode write cycle timing motorola mode read cycle timing t17 ale t19 t29 t28 t26 ad<7:0> iowc* csin* t30 t18 a<1:0> d<7:0> a<1:0> t20 t31 t22 t23 a<1:0> t37 csin* rw* ds* t35 t32 t34 t40 t36 t39 d<7:0> t38 t33 t17 ale t19 t27 t21 t26 ad<7:0> iorc* csin* t24 t18 a<1:0> d<7:0> a<1:0> t20 t25 t22 t23
p reliminary W6690 - 70 - motorola mode write cycle timing pcm interface timing 1) notes 1. these drawings are not to scale. 2. the frequency of pbck is 1536 khz which includes 24 channels of 64 kbps data. the pfck1 and pfck2 are located at channel 1 and channel 13, each with a 8 x pbck duration. a<1:0> t43 csin* rw* ds* t35 t32 t34 t45 t42 t44 d<7:0> t41 t33 pbck 2) (1.536mhz) pfck1 2) pfck2 2) ptxd prxd 24 chs ch 1 ch 13 port1 port1 port2 port2 port1 port1
p reliminary W6690 publication release date: march 1998 - 71 - revision a1 detailed pcm timing eeprom timing parameter parameter descriptions min. max. remarks t1 aen* valid before iorc*, iowc* asserted 100 unit: ns t2 a<1:0> valid before iorc*, iowc* asserted 88 t3 iorc*, iowc* asserted before iorc*, iowc* negated t3a i/o access with 3 clocks 166 t3b i/o access with 6 clocks 530 t3c i/o access with 7 clocks 650 t4 iorc*, iowc* negated before aen* invalid 30 t5 iorc*, iowc* negated before a<1:0> invalid 32 pbck pfck1 pfck2 ptxd prxd t46 t47 t48 t49 t50 t51 t52 t53 a5 a4 a1 a0 ..... d15 d14 d1 d0 t54 t55 t56 t56 t57 t57 t58 t60 t59 epsk epcs epsd .....
p reliminary W6690 - 72 - parameter parameter descriptions min. max. remarks t6 nows* asserted after iorc*, iowc* valid 20 t7 nows* deasserted after iorc*, iowc* invalid 20 t8 iorc* asserted to read data valid 50 t9 iorc* negated to read data invalid 0 t10 iorc* negated to data bus float 30 t11 write data valid before iowc* asserted 0 t12 iowc* negated to write data invalid 0 t13 a<15:0> valid to cso* assserted 20 t14 a<15:0> invalid to cso* deasserted 20 t15 csin* valid before iorc*, iowc* asserted 10 t16 csin* invalid after iorc*, iowc* deasserted 0 t17 ale pulse width 50 t18 address setup time to ale 15 t19 address hold time from ale 10 t20 address setup time to iorc*, iowc* 0 t21 iorc* pulse width 110 t22 csin* setup time to iorc*, iowc* 0 t23 csin* hold time from iorc*, iowc* 0 t24 data output delay from iorc* 50 t25 data float from iorc* 25 t26 ale guard time 15 t27 iorc* recovery time 70 t28 iowc* pulse width 60 t29 iowc* recovery time 70 t30 data setup time to iowc* 35 t31 data hold time from iowc* 10 t32 address setup time to ds* 25 t33 address hold time from ds* 10 t34 csin* setup time to ds* 10 t35 csin* hold time from ds* 10 t36 ds* read pulse width 110 t37 ds* read recovery time 70 t38 rw* setup time to ds* read 0
p reliminary W6690 publication release date: march 1998 - 73 - revision a1 parameter parameter descriptions min. max. remarks t39 data output delay from ds* 110 t40 data hold time from ds* 25 t41 rw* setup time to ds* write 0 t42 ds* write pulse width 60 t43 ds* write recovery time 70 t44 write data setup time to ds* 35 t45 write data hold time from ds* 10 t46 pbck pulse high 260 t47 pbck pulse low 260 t48 frame clock asserted from pbck 20 t49 ptxd data delay from pbck 20 t50 frame clock deasserted from pbck 20 t51 ptxd hold time from pbck 10 t52 prxd setup time to pbck 20 t53 prxd hold time from pbck 10 t54 epsk low 2500 t55 epsk high 2500 t56 epcs output delay 30 t57 epsd output delay 30 t58 epsd tri-state delay 30 t59 epsd input setup time 30 t60 epsd input hold time 30 9.5 ac timing test conditions t a = 0 to 70 c, v dd = 5 v 5 % inputs are driven to 2.4v for logical 1 and 0.4v for logical 0. measurements are made at 2.0v for logical 1 and 0.8v for logical 0. the ac testing input/output waveforms are shown below: test point 2.0 0.8 2.0 0.8 2.4 0.4 device under test c load = 150 pf
p reliminary W6690 - 74 - 10. package dimensions 10.1 68-pin plcc 68 61 60 44 43 27 26 10 9 1 l c 1 b 2 a h d d e b e h e y a a 1 seating plane d g g e symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a 1 2 e b 1 h d g g d e 0.020 0.143 0.026 0.016 0.006 0.949 0.895 0.980 0.090 0.148 0.028 0.018 0.008 0.954 0.915 0.990 0.100 0.050 0.185 0.153 0.032 0.022 0.012 0.959 0.935 1.000 0.110 0.004 0.51 3.63 0.66 0.41 0.15 24.10 22.73 24.90 2.29 3.76 0.71 0.46 0.20 24.23 23.24 25.15 2.54 1.27 4.70 3.89 0.81 0.56 0.30 24.36 23.75 25.40 2.79 0.10 10 0 0 10 0.044 0.056 1.12 1.42 24.36 24.23 24.10 0.959 0.954 0.949 23.75 23.24 22.73 0.935 0.915 0.895 25.40 25.15 24.90 1.000 0.990 0.980 q q
p reliminary W6690 publication release date: march 1998 - 75 - revision a1 10. package dimensions, continued 10.2 100-pin qfp (14 20 1.4 mm footprint 2.0 mm) e h y a a2 seating plane l l 1 see detail f controlling dimension: millimeters a1 e d h d e b c 0.08 0 7 0 0.003 1.00 0.75 16.10 0.60 16.00 0.45 15.90 0.039 0.030 0.870 0.634 0.024 0.866 0.630 0.018 0.862 0.626 0.65 20.10 14.10 0.20 0.38 1.45 20.00 14.00 1.40 19.90 13.90 0.10 0.22 1035 0.791 0.555 0.008 0.015 0.057 0.787 0.551 0.055 0.026 0.783 0.547 0.004 0.009 0.053 symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h d h e l y a a l 1 1 2 e 0.013 0.006 0.15 0.32 21.90 22.00 22.10 7 0.020 0.032 0.498 0.802 0.10 0.05 0.002 0.004 0.006 0.15 q q
p reliminary W6690 - 76 - headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792646 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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